• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• 반도체디스플레이기술학회지
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• 제4권2호
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• pp.11-14
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• 2005

In plasma processing reactors, it is common practice to control plasma density and ion bombardment energy by manipulating excitation voltage and frequency. In this paper, a dually excited capacitively coupled rf plasma reactor is self-consistently simulated with a three moment model. Effects of phase differences between primary and secondary voltage waves, simultaneously modulated at various combinations of commensurate frequencies, on plasma properties are investigated. The simulation results show that plasma potential and density as well as primary self-dc bias are nearly unaffected by the phase lag between the primary and the secondary voltage waves. The results also show that, with the secondary frequency substantially lower than the primary frequency, secondary self·do bias remains constant regardless of the phase lag. As the secondary frequency approaches to the primary frequency, however, the secondary self-dc bias becomes greatly altered by the phase lag, and so does the ion bombardment energy at the secondary electrode. These results demonstrate that ion bombardment energy can be more carefully controlled through plasma simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.513-514
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• 2005

In plasma processing reactors, it is common practice to control plasma density and ion bombardment energy by manipulating excitation voltage and frequency. In this paper, a dually excited capacitively coupled rf plasma reactor is self-consistently simulated with a three moment model. Effects of phase differences between primary and secondary voltage waves, simultaneously modulated at various combination of commensurate frequencies, on plasma properties are investigated. The simulation results show that plasma potential and density as well as primary self-dc bias are nearly unaffected by the phase lag between the primary and the secondary voltage waves. The results also show that, with the secondary frequency substantially lower than the primary frequency, secondary self-dc bias remains constant regardless of the phase lag. As the secondary frequency approaches to the primary frequency, however, the secondary self-dc bias becomes greatly altered by the phase lag, and so does the ion bombardment energy at the secondary electrode. These results demonstrate that ion bombardment energy can be more carefully controlled through plasma simulation.

• Journal of Magnetics
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• 제15권3호
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• pp.132-137
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• 2010

Plasma etching of $SiO_2$ contact holes was statistically analyzed by a fractional factorial experimental design. The analysis revealed the dependence of the etch rate and DC self-bias voltage on the input factors of the magnetically enhanced reactive ion etching reactor, including gas pressure, magnetic field, and the gas flow rates of $CHF_3$, $CF_4$, and Ar. Empirical models of the DC self-bias voltage and etch rate were obtained. The DC self-bias voltage was found to be determined mainly by the operating pressure and the magnetic field, and the etch rate was related mainly to the pressure and the flow rates of Ar and $CHF_3$.

• 전기학회논문지
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• 제57권7호
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• pp.1218-1222
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• 2008

We investigate the effect of rise time of a pulse bias voltage on atmospheric plasma generation. With the faster rise time of the pulse bias, the glow discharge appears to be more uniformly generated along the electrodes. I-V measurement confirms that higher loading power can be obtained using the faster rise time. A new understanding for atmospheric plasma generation at a micro-gap electrode is suggested.

• 한국재료학회지
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• 제4권1호
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• pp.9-23
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• 1994

Multitarget bias cosputter deposition(MBCD)에 의해 저온($200^{\circ}C$)에서 NaCI(100)상에 정합$CoSi_2$를 성장시켰다. X-선회절과 투과전자현미경에 의해 증착온도와 기판 bias전압에 따른 각각 silicide의 상전이와 결정성을 관찰하였다. Metal induced crystallization(MIC) 과 self bias 효과에 의해 $200^{\circ}C$에서 기판전압을 인가하지 않은 경우에도 결정질 Si이 성장하였다. MIC현상을 이론 및 실험적으로 고찰하였다. 관찰된 상전이는 $Co_2Si \to CoSi \to Cosi_2$로서 유효생성열법칙에 의해 예측된 상전이와 일치하였다. 기판 bias전압 인가시 발생한 이온충돌에 의한 충돌연쇄혼합(collisional cascade mixing), 성장박막 표면의 in situ cleaning, 핵생성처(nucleation site)이 증가로 인하여 상전이, CoSi(111)우선방위, 결정성은 증착온도에 비해 기판bias전압에 더 큰 영향을 받았다. $200^{\circ}C$에서 기판 bias전압을 증가시킴에 따라 이온충돌에 의한 결정입성장이 관찰되었으며, 이를 이온충독파괴(ion bombardment dissociation)모델에 의해 해석하였다. $200^{\circ}C$에서의 기판 bias전압증가에 따른 결정성변화를 정량적으로 고찰하기 위해 Langmuir탐침을 이용하여 $E_{Ar},\; \alpha(V_s)$를 계산하였다.

• Journal of information and communication convergence engineering
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• 제7권2호
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• 한국표면공학회지
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• 제32권2호
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• pp.93-99
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• 1999

Surface polymer layer formed on the silicon wafer during the oxide overetching using $C_4F_8$/ helicon wave plasmas and their characteristics were investigated using spectroscopic elipsometry, X-ray photoelectron spectroscopy, and secondary ion mass spectrometry. Overetch percentage and dc-self bias voltage were varied to investigate the effects on the characteristics of the polymers remaining on the overetched silicon surface. The increase of bias voltage from -80 volts to -120 volts increased the C/F ratio and carbon bondings such as C-C, $C-CF_x$/, and C-Si in the polymer while reducing the thickness of the polymer layer. However, the increase of the overetch percentage from 50% to 100% did not change the composition of the polymer layer and the carbon bondings in the polymer layer remained same even though it increased the polymer thickness. The polymer layer formed at the higher dc-self bias voltage was more difficult to be removed by the following various post-etch treatments compared to that formed at the longer overetch percentage.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권5호
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• pp.220-229
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• 2004

We have examined a technique of one-dimensional (1D) fluid modeling for radio-frequency Ar capacitively coupled plasmas (CCP) between unequal-sized powered and grounded electrodes. In order to simulate a practical CCP reactor configuration with a grounded side wall by the 1D model, it has been assumed that the discharge space has a conic frustum shape; the grounded electrode is larger than the powered one and the discharge space expands with the distance from the powered electrode. In this paper, we focus on how much a 1D model can approximate a 2D model and evaluate their comparisons. The plasma density calculated by the 1D model has been compared with that by a two-dimensional (2D) fluid model, and a qualitative agreement between them has been obtained. In addition, 1D and 2D calculation results for another reactor configuration with equal-sized electrodes have also been presented together for comparison. In the discussion, four CCP models, which are 1D and 2D models with symmetric and asymmetric geometries, are compared with each other and the DC self-bias voltage has been focused on as a characteristic property that reflects the unequal electrode surface areas. Reactor configuration and experimental parameters, which the self-bias depends on, have been investigated to develop the ID modeling for reactor geometry with unequal-sized electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).