• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.11-14
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• 2005

In plasma processing reactors, it is common practice to control plasma density and ion bombardment energy by manipulating excitation voltage and frequency. In this paper, a dually excited capacitively coupled rf plasma reactor is self-consistently simulated with a three moment model. Effects of phase differences between primary and secondary voltage waves, simultaneously modulated at various combinations of commensurate frequencies, on plasma properties are investigated. The simulation results show that plasma potential and density as well as primary self-dc bias are nearly unaffected by the phase lag between the primary and the secondary voltage waves. The results also show that, with the secondary frequency substantially lower than the primary frequency, secondary self·do bias remains constant regardless of the phase lag. As the secondary frequency approaches to the primary frequency, however, the secondary self-dc bias becomes greatly altered by the phase lag, and so does the ion bombardment energy at the secondary electrode. These results demonstrate that ion bombardment energy can be more carefully controlled through plasma simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.513-514
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• 2005

In plasma processing reactors, it is common practice to control plasma density and ion bombardment energy by manipulating excitation voltage and frequency. In this paper, a dually excited capacitively coupled rf plasma reactor is self-consistently simulated with a three moment model. Effects of phase differences between primary and secondary voltage waves, simultaneously modulated at various combination of commensurate frequencies, on plasma properties are investigated. The simulation results show that plasma potential and density as well as primary self-dc bias are nearly unaffected by the phase lag between the primary and the secondary voltage waves. The results also show that, with the secondary frequency substantially lower than the primary frequency, secondary self-dc bias remains constant regardless of the phase lag. As the secondary frequency approaches to the primary frequency, however, the secondary self-dc bias becomes greatly altered by the phase lag, and so does the ion bombardment energy at the secondary electrode. These results demonstrate that ion bombardment energy can be more carefully controlled through plasma simulation.

• Journal of Magnetics
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• v.15 no.3
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• pp.132-137
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• 2010

Plasma etching of $SiO_2$ contact holes was statistically analyzed by a fractional factorial experimental design. The analysis revealed the dependence of the etch rate and DC self-bias voltage on the input factors of the magnetically enhanced reactive ion etching reactor, including gas pressure, magnetic field, and the gas flow rates of $CHF_3$, $CF_4$, and Ar. Empirical models of the DC self-bias voltage and etch rate were obtained. The DC self-bias voltage was found to be determined mainly by the operating pressure and the magnetic field, and the etch rate was related mainly to the pressure and the flow rates of Ar and $CHF_3$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1218-1222
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• 2008

We investigate the effect of rise time of a pulse bias voltage on atmospheric plasma generation. With the faster rise time of the pulse bias, the glow discharge appears to be more uniformly generated along the electrodes. I-V measurement confirms that higher loading power can be obtained using the faster rise time. A new understanding for atmospheric plasma generation at a micro-gap electrode is suggested.

• Korean Journal of Materials Research
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• v.4 no.1
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• pp.9-23
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• 1994

Epitaxial $CoSi_2$ layer has been grown on NaCl(100) substrate at low deposition temperature($200^{\circ}C$) by multitarget bias cosputter deposition(MBCD). The phase sequence and crystallinity of deposited silicide as a function of deposition temperature and substrate bias voltage were studied by X-ray diffraction(XRD) and transmission electron microscopy(TEM) analysis. Crystalline Si was grown at $200^{\circ}C$ by metal induced crystallization(M1C) and self bias effect. In addition to, the MIC was analyzed both theoretically and experimentally. The observed phase sequence was $Co_2Si \to CoSi \to Cosi_2$ and was in good agreement with that predicted by effective heat of formation rule. The phase sequence, the CoSi(l11) preferred orientation, and the crystallinity had stronger dependence on the substrate bias voltage than the deposition temperature due to the collisional cascade mixing, the in-situ cleaning, and the increase in the number of nucleation sites by ion bombardment of growing surface. Grain growth induced by ion bombardment was observed with increasing substrate bias voltage at $200^{\circ}C$ and was interpreted with ion bombardment dissociation model. The parameters of $E_{Ar}\;and \alpha(V_s)$ were chosen to properly quantify the ion bombardment effect on the variation in crystallinty at $200^{\circ}C$ with increasing substrate bias voltage using Langmuir probe.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• Journal of the Korean institute of surface engineering
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• v.32 no.2
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• pp.93-99
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• 1999

Surface polymer layer formed on the silicon wafer during the oxide overetching using $C_4F_8$/ helicon wave plasmas and their characteristics were investigated using spectroscopic elipsometry, X-ray photoelectron spectroscopy, and secondary ion mass spectrometry. Overetch percentage and dc-self bias voltage were varied to investigate the effects on the characteristics of the polymers remaining on the overetched silicon surface. The increase of bias voltage from -80 volts to -120 volts increased the C/F ratio and carbon bondings such as C-C, $C-CF_x$/, and C-Si in the polymer while reducing the thickness of the polymer layer. However, the increase of the overetch percentage from 50% to 100% did not change the composition of the polymer layer and the carbon bondings in the polymer layer remained same even though it increased the polymer thickness. The polymer layer formed at the higher dc-self bias voltage was more difficult to be removed by the following various post-etch treatments compared to that formed at the longer overetch percentage.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.5
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• pp.220-229
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• 2004

We have examined a technique of one-dimensional (1D) fluid modeling for radio-frequency Ar capacitively coupled plasmas (CCP) between unequal-sized powered and grounded electrodes. In order to simulate a practical CCP reactor configuration with a grounded side wall by the 1D model, it has been assumed that the discharge space has a conic frustum shape; the grounded electrode is larger than the powered one and the discharge space expands with the distance from the powered electrode. In this paper, we focus on how much a 1D model can approximate a 2D model and evaluate their comparisons. The plasma density calculated by the 1D model has been compared with that by a two-dimensional (2D) fluid model, and a qualitative agreement between them has been obtained. In addition, 1D and 2D calculation results for another reactor configuration with equal-sized electrodes have also been presented together for comparison. In the discussion, four CCP models, which are 1D and 2D models with symmetric and asymmetric geometries, are compared with each other and the DC self-bias voltage has been focused on as a characteristic property that reflects the unequal electrode surface areas. Reactor configuration and experimental parameters, which the self-bias depends on, have been investigated to develop the ID modeling for reactor geometry with unequal-sized electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).