• 한국통신학회논문지
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• 제21권12호
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• pp.3256-3264
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• 1996

This paper presents an efficient VLSI architecture for transposing matris in high speed. In the case of transposing N*N matrix, N$^{2}$ numbers of transposition cells are configured as regular and spuare shaped structure, and pipeline structure for operating each transposition cell in paralle. Transposition cell consists of register and input data selector. The characteristic of this architecture is that the data to be transposed are divided into several bundles of bits, then processed serially. Using the serial transposition of divided input data, hardware complexity of transpositioncell can be reduced, and routing between adjacent transposition cells can be simple. the proposed architecture is designed and implemented with 0.5 .mu.m VLSI library. As a result, it shows stable operation in 200 MHz and less hardware complexity than conventional architectures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2767-2769
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• 1999

This paper introduces a new rotor position estimation algorithm for the SRM, based on the magnetizing curves only at aligned and unaligned rotor positions. Through basic test method, the complete SRM magenetizing characterization is first constructed, and then used to estimate the rotor position. And also, the optimized phase is selected by phase selector. To demonstrate the promise of this approach. the proposed rotor position estimation algorithm is simulated for variable speed range.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.201-203
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• 1993

Recently, micro-scaled cell fusion system in the bioiogical cell fusion is preferred to Nacro-scaled one by dint of microelectronic processes. The microfabricated cell fusion system has its components such as fusion chamber, selector and detector. In this paper, we describe the design rules of the micro-fabricated cell fusion system using dielectrophoretic force and analyze its components using finite element method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• 대한기계학회논문집B
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• 제29권8호
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• pp.903-910
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• 2005

Inverse radiation problems are solved for estimating the boundary conditions such as temperature distribution and wall emissivity in axisymmetric absorbing, emitting and scattering medium, given the measured incident radiative heat fluxes. Various regularization methods, such as hybrid genetic algorithm, conjugate-gradient method and finite-difference Newton method, were adopted to solve the inverse problem, while discussing their features in terms of estimation accuracy and computational efficiency. Additionally, we propose a new combined approach that adopts the hybrid genetic algorithm as an initial value selector and uses the finite-difference Newton method as an optimization procedure.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2040-2043
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• 2003

General-purpose MPEG-2 video transcoders must be able to achieve any conversion between 18 ATSC (Advanced television system committee) video formats for DTV (digital television), e.g., scan format, size format, and frame rate format conversion. Especially, scan format conversion is hard to implement because frame rate and size format conversion often happen together. This paper proposes a fast motion estimation(ME) algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MV's) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MV's by using a weighted median selector. Simulation results show that the proposed ME algorithm reduces significantly transcoding complexity with a minor PSNR degradation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.912-913
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• 2008

In this paper, peak detector of generator output voltage and variable gain controller is introduced for the fast dynamic response. The general r.m.s. detecting signal of generator has inherent time delay from the actual signal. So the dynamic response of generator using conventional PID controller has some problem in sudden load change. In order to overcome this problem, the peak detector and signal selector with variable gain controller is used in this paper. The proposed control scheme is verified from experimental test of 200kW diesel engine-generator.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2008년도 춘계학술대회 논문집
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• pp.17-20
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• 2008

본 논문에서는 After-market에서 자동차 헤드라이트 상 하향 빔 전환 시스템으로 주로 사용하고 있는 solenoid 방식의 여러 문제점을 개선하기 위하여 차량용 릴레이를 이용한 HID램프의 헤드라이트 상 하향 전환 컨트롤 방식를 제안하였다. 특히, 차종에 따라 달라지는 상 하향 빔 전환 입력신호에 대하여 릴레이가 일정하게 상 하향 동작을 할 수 있는 signal selector회로를 구성하고, 두 개의 램프를 relay로 전환하는 방식을 채택함으로서 그 동안 자동차 하우징 구조상 기존 H4 타입에만 국한되어 오던 차량용 HID램프의 헤드라이트 상 하향 빔 전환 시스템을 H1, H3, H7, H11, 9004, 9006, 9007 등 다른 베이스타입의 벌브에도 적용이 가능하도록 하여 우수한 범용성을 갖도록 하였다.

• 한국통신학회논문지
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• 제13권6호
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• pp.501-509
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• 1988

토로이달코아와 상호절연된 撚線을 사용하여 30MHz~90MHz대역에 사용할 수 있는 새로운 형태의 임피던스 정합용변성기를 설계하고 제작하였다. 측정결과 전주파수대역에서 삽입손실 1.2[dB]이하, 정재파비2.0이하이었으며 100[%]의 대역폭으로 비교적 좋은 특성을 보여주고 있다. 제안한 변성기는 간편하고 제작이 용이하기 때문에 종래의 주파수절환형태의 정합회로를 대체하여 사용이 가능하리라 생각된다.