• Journal of Crop Science and Biotechnology
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• v.11 no.3
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• pp.171-176
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• 2008

The agronomic traits, such as days to flowering and maturity, plant height, 100-seed weight and seed filling period, are quantitatively inherited and important characters in soybean(Glycine max L. Merr.). A total of 126 $F_5$ recombinant inbred lines(RILs) developed from the cross of PI 171451$\times$Hwaeomputkong were used to identify quantitative trait loci(QTLs) for days to flowering(FD), days to maturity(MD), plant height(PH), 100-seed weight(SW), number of branches(NB) and seed filling period(FP). A total of 136 simple sequence repeat(SSR) markers segregated in a RIL population were distributed over 20 linkage groups(LGs), covering 1073.9 cM of the soybean genome with the average distance between adjacent markers of 7.9 cM. Five independent QTLs were identified for FD, three for MD, two for PH, three for SW, one for NB and one for FP. Of these, three QTLs were related to more than two traits of FD, MD, PH, NB and FP and mapped near the same positions on LGs H and O. Thus, these traits could be correlated with biologically controlled major QTLs in this soybean RIL population.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.51 no.6
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• pp.534-538
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• 2006

The effects of Rhizobium inoculant, compost, and nitrogen on nodulation, growth, dry matter production, yield attributes, and yield of pea (Pisum sativum) var, IPSA Motorshuti-3 were assessed by a field experiment. Among the treatments Rhizobium inoculant alone performed best in recording number and dry weight of nodules/plant. The highest green seed yield of 8.38 ton/ha (36.9% increase over control) and mature seed yield of 2.97 ton/ha (73.7% increase over control) were obtained by the application of 90 kg N/ha. The effects of 60 kg N/ha, Rhizobium inoculant alone and Rhizobium inoculant along with 5 ton compost/ha were same as the effect of 90 kg N/ha in recording plant height, root length, dry weight of shoot, and root both at preflowering and pod filling stages, number of mature pods/plant, number of mature seeds/pod, 1000-seed weight, green, and mature seed yields of pea.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of Information Processing Systems
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• v.19 no.4
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• pp.540-553
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• 2023

The hollow letter CAPTCHA (Completely Automated Public Turing test to tell Computers and Humans Apart) is an optimized version of solid CAPTCHA, specifically designed to weaken characteristic information and increase the difficulty of machine recognition. Although convolutional neural networks can solve CAPTCHA in a single step, a good attack result heavily relies on sufficient training data. To address this challenge, we propose a seed filling algorithm that converts hollow characters to solid ones after contour line restoration and applies three rounds of detection to remove noise background by eliminating noise blocks. Subsequently, we utilize a support vector machine to construct a feature vector for recognition. Security analysis and experiments show the effectiveness of this algorithm during the pre-processing stage, providing favorable conditions for subsequent recognition tasks and enhancing the accuracy of recognition for hollow CAPTCHA.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.43 no.3
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• pp.147-151
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• 1998

The conductivity test is a measure of electrolytes leakage from plant tissue. The shorter the maturation period after heading was the greater electrical conductivity (EC) of rice seed. The polymer-coated seed was not different in EC compared with non-coated seed. As soaking time of rice seed increased, EC increased gradually. The EC varied from 9.9 to 20.7$\mu$S $cm^{-1}g^{-l}$ for control plots and from 21.3 to 41.7$\mu$S $cm^{-1}g^{-l}$ for heat-killed seeds which were produced by autoclaving seeds at 121$^{\circ}C$ for 20 minutes. The germination speed (the rate of 5th day) of rice seed was 94% at control plot, 83% at low temperature and 20% at high temperature. Besides, germination percentage was 95% for the control, 92% for the low temperature treatment and 39% for the high temperature treatment. The EC was negatively correlated (r=-0.771$^{**}$) with germination percentage at low temperature. Water uptake in seeds of 30, 40, 50 days after heading (DAH) was greater than that of 20 DAH. Plant height of seedlings was 9.84 cm for the control but 4.32 cm for the high temperature treatment, and the tallest for polymer-coated seed. Dry weight of seedlings was 0.841 g for the control and 0.287 g at high temperature. Besides, the polymer-coated seed was heavier than non-coated seed. The number of roots was largest from 40 to 50 DAH and polymer-coated seed, but was decreased from 20 to 30 DAH. The length of roots was 20.52 cm at control plot and 19.89 cm polymer-coated seed but 8.68 cm for the low temperature treatment and 7.28 cm for the high temperature treatment.

• Proceedings of the Korean Society of Crop Science Conference
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• 1993.10a
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• pp.20-21
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• 1993