• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.81-84
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• 2002

This paper presents the real-time PCB(Printed circuit board) inspection system that can detect thin open/short error using the line scan camera. After a overall introduction of our system, the outline of our inspection methods are described. The goal of our inspection system is the real time and detailed inspection using the line scan camera. To perform inspection processing in real-time, we utilize double buffering structure. In order to solve the problem of unexpectable pixels of PCB, we propose melting process which eliminates unexpectable pixels of PCB. The design and development of our prototype of PCB ins- pection system is discussed and test results are presented to show the effectiveness of the developed inspection algorithm.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.333-334
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• 2007

We propose a path planning method to decrease a inspection lead time of line scan camera in SMT(surface mount technology) in-line system. The inspection window area of printed circuit board should be minimized to consider the FOV(field of view) of line scan camera so that line scan inspector is going to find a optimal solution of path planning. We propose one of the hierarchical clustrering algorithm for a given board. Comparative simulation results are presented to verify the usefulness of proposed method.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.4
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• pp.370-376
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• 2008

Power capacitors is widely used for power factor correction and component of passive filter in the user power systems. Recently, application of non-linear load is gradually increased. Non-linear load produces harmonic components of current. There are series resonance and parallel resonance when capacitors are applied in the user electrical application. If this harmonic component matches resonance, voltage and current is magnified and has severely an influences on capacitor. This paper purposes a new method for the magnitude of voltage and current by the frequency scan analysis without equivalent circuit for the actual circuit at the resonance condition.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.219-225
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• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.55-65
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• 2004

In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1405-1408
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• 2008

Synchronization signal circuit system for low cross-talk stereoscopic display. We proposed the employment of the scanning beams of any adjacent scanning regions gradually scan from upper to down direction of the LED backlight panel.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.239-242
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• 2005

A high speed address recovery technique for AC plasma display Panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, the technique shows the minimum address power consumption according to various displayed images, different from Prior methods operating in fixed mode regardless of images. Test results with 50" HD single-scan PDP(resolution = 1366$\times$768) show that less than 350ns of recovery time is successfully accomplished and about 54% of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.4
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• pp.406-414
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• 1997

A real-time inspection system is developed using line scan cameras. Several improved algorithms are proposed for real-time detection of defects in this automated inspection system. The major improved algorithms include the preprocessing, the threshold decision, and the clustering algorithms. The preprocessing algorithms are for exact binarization and the threshold decision algorithm is for fast detection of defects in 1-D binary images. The clustering algorithm is also developed for fast classifying of the defects. The system is applied to PCBs(Printed Circuit Boards) inspection. The typical defects in PCBs are pits, dent, wrinkle, scratch, and black spots. The results show that most defects are detected and classified successfully.