• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.574-580
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• 2013

Compared with the TWS(Track While Scan) tracking that uses scan-to-scan correlation at search illuminations for targets track, a phased array radar can use adaptive tracking which assigns additional track illuminations and the track formation range can be improved as a result. In this paper, an adaptive tracking, the search and track illuminations of a target are synchronized such that the extra illuminations are evenly distributed between the search illuminations, is proposed. Markov chain and track formation range for the proposed adaptive tracking are shown with them for the conventional TWS. The simulation result shows that the proposed adaptive tracking has improved track formation range by 27.6 % compared with the conventional TWS tracking under same track confirmation criterion.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.669-671
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• 1998

Due to the serial nature of scan chains, the use of the boundary scan chain leads the high application costs. And with 3-state net, it is important to avoid enabling the two drivers in a net. In this paper, the new test method for 3-state nets in the multiple boundary scan chains is presented. This method configures the boundary scan cells as multiple scan chains and the test application time can be reduced. Also three efficient algorithms are proposed for testing the interconnects in a board without the collision of the test data in 3-state nets.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1191-1195
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• 2009

We present the efficient test wrapper design methodology considering the layout distance of scan chain. To test the scan chains in SoC, the scan chains must be assigned to external TAM(Test Access Mechanism) lines. The scan chains in IP were placed and routed without any timing violation at normal mode. However, in test mode, the scan chains have the additional layout distance after TAM line assignment, which can cause the timing violation of flip-flops in scan chains. This paper proposes a new test wrapper design considering layout distance of scan chains with timing violation free.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.4
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• pp.306-314
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• 2013

Automatic tracking in cluttered environment requires the initiation and maintenance of tracks, and track existence probability of true track is kept by Markov Chain Two model of target existence propagation. Unlike Markov Chain One model for target existence propagation, Markov Chain Two model is made up three hypotheses about target existence event which are that the target exist and is detectable, the target exists and is non-detectable through occlusion, and the target does not exist and is non-detectable according to non-existing target. In this paper we present multi-scan single target tracking algorithm based on the target existence, which call the Integrated Track Splitting algorithm with Markov Chain Two model in imaging sensor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.124-130
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• 2014

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.