• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• Journal of The Korean Association For Science Education
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• v.24 no.3
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• pp.612-620
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• 2004

The purpose of this study was to investigate how middle and high school students represent circuit diagrams with different shapes but electrically same. What prototypes of circuit which students possessed were, how students represented the connection of resistors, and what criteria used while grouping the circuit diagrams were investigated. The participants were 10 middle and 10 high school students. The results show that they represented the circuit diagrams by the geometrical resistor configurations rather than physics principles, not considering the presence of a junction or a battery on the branch. This representation was constrained by the circuit prototypes. Middle and High school students seems to have the own way of representing circuit diagrams without considering physics principles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.16-22
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• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.37-42
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• 2004

In the electronic components and devices fabrication, thin film resistors with low TCR (temperature coefficient of resistance) and high precision have been used over 3 ㎓ microwave in recent years. Ni-Cr alloys thin films resistors is one of the most commonly used resistive materials because they have low TCR and highly stable resistance. In this work, we fabricated thin film resistors using Evanohm alloys target(72Ni-20Cr-3Al-4Mn-Si) of S-type with excellent resistors properties by RF-sputtering. Also we reported the best annealing condition of thin film resistors for microwave to observe microstructure and electronic properties of thin film according to annealing conditions($200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$)

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.1-9
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• 1989

In binary digital transmission system the band-limiting is required for the better transmission efficiency. But in the case of band-limiting the intersymbol-interference (ISI) usually takes place. In this paper, in an attempt to design band-limiting filter which has minimum ISI and maximum stop-band loss, first, making use of analog filter by combining Binary Transversal Filter (BTF) and analog filter (4th Butterworhfilter), we found the value that minimizes ISI phenomenon by getting step response of rectangular pulse resulting from BTF in time domain. Second, we found filter characteristic we want to in frequency domain for band-limiting and minimized the error. And then we obtained resistor value (Tap coefficient) in order to design algorithm for optimum filter. Also we showed the example of simulation in case we established the resistors with 3,5 and 7 respectively. With 7 resistors set, we identified that the ripple of about minus 30dB was taken place.