• Journal of the Korean Society for Precision Engineering
• /
• v.29 no.9
• /
• pp.971-977
• /
• 2012

Redundant actuated parallel kinematic machines (PKMs) have been widely researched to increase stiffness of PKMs. This paper presents theoretical analyses on the stiffness of non-redundant and redundant actuated PKM. Stiffness of each mechanism is defined by summation of actuator and structural stiffness; the actuator stiffness is determined from displacements of actuators, and the structural stiffness is determined from deformations of links by external forces. Calculated actuator and structural stiffness of non-redundant PKM show same distribution in entire workspace. On the contrary, the actuator and the structural stiffness of a redundant PKM has very different distribution in the workspace; so, we conclude the structural stiffness of redundant PKM should be considered to design the redundant PKM. The results can be used to design and analyze non-redundant and redundant PKMs.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.1613-1616
• /
• 1997

In order to develop a human hand mechanism, a 5-bar finger with redundant actuation is designed and implemented. an optimal set of acutator locations and link lengths for the case of one redundant actuator is obtained by employing a composite design index which simulataneously consider several performance indices such as workspace, isotropic index, and force transmission ratio. Each joing is driven by an compact actuator mechanism having ultrasonic motor and a gear set with poeneiometer an controlled by VME Bus-based control system.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.523-524
• /
• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.55 no.11
• /
• pp.491-494
• /
• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Journal of the military operations research society of Korea
• /
• v.5 no.2
• /
• pp.73-80
• /
• 1979

In military applications of equipment, it is of the utmost importance that the equipment operates without breakdown for a specified length of time. We can increase the reliability of a system by adding redundant components to the basic nonredundant system. This study introduces a dynamic programming algorithm of finding optimum redundant design that maximizes the system reliability with constraints.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2011.06a
• /
• pp.51-52
• /
• 2011

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.3
• /
• pp.517-524
• /
• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• Journal of the Korean Society for Precision Engineering
• /
• v.13 no.4
• /
• pp.97-108
• /
• 1996

Optimal design of fault-tolerant, spatial type redundant manipulators is treated in this paper. Design objective is to guarantte three degree-of -freedom translational motions in the task space, upon failure of one arbitrary joint of 4 degree-of-freedom manipulators. Noticing the nonfault-tolerant characteristics of current, wrist-type industrial manipulators, five different fault-tolerant spatial-type manipulators which have 4 degree-of-freedom structures with one joint redundancy are suggested. Faault-tolerant character-sitics of two redundant manipulators anr investigated based on the analysis of the self-motion and the null-space elements. Finally, in order to maximize the fault-tolerant capability, optimal design is performed for a spatial-type manipulator with respect to the global isotropic index, and the performance enhancement of the optimized case is shown by simulation.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.148-151
• /
• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Journal of Institute of Control, Robotics and Systems
• /
• v.3 no.5
• /
• pp.482-489
• /
• 1997

This paper presents the analysis of the kinematics and dynamics of redundant parallel manipulators, and provides design guides for advanced parallel mainpulators with high performance. Three types of redundancies are considered which include the redundancies in serial chain, joint actuation, and parallelism. First, the kinematic and dynamic models of a redundant parallel manipulator are obtained in both joint and Cartesian spaces, and the kinematic and dynamic manipulabilities are defined for the performance evaluation. The effects of the three types of redundancies on the kinematic and dynamic performance of a parallel manipulator are then analyzed and compared, providing a set of guides for the design of advanced parallel manipulators. Finally, the simulation results using planer parallel manipulators are given.