• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.172-183
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• 2010

Virtual memory systems (VM) reduce disk I/Os caused by page faults using page prefetching, which reads pages together with a desired page at a page fault in a single disk I/O. Operating systems including 4.4BSD attempt to prefetch as many pages as possible at a page fault regardless of page access patterns of applications. However, such an approach increases a disk access time taken to service a page fault when a high portion of the prefetched pages is not referenced. More seriously, the approach can cause the memory pollution, a problem that prefetched pages not to be accessed evict another pages that will be referenced soon. To solve these problems, we propose an adaptive page prefetching control scheme (APC), which periodically monitors access patterns of prefetched pages in a process unit. Such a pattern is represented as the ratio of referenced pages among prefetched ones before they are evicted from memory. Then APC uses the ratio to adjust the number of pages that 4.4BSD VM intends to prefetch at a page fault. Thus APC allows 4.4BSD VM to prefetch a proper number of pages to have a better effect on reducing disk I/Os, though page access patterns of an application vary in runtime. The experiment of our technique implemented in FreeBSD 6.2 shows that APC improves the execution times of SOR, SMM, and FFT benchmarks over 4.4BSD VM by up to 57%.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.2
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• pp.107-115
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• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Korean Journal of Computational Design and Engineering
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• v.13 no.1
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• pp.1-7
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• 2008

Data compression becomes increasingly an important issue for reducing data storage spaces as well as transmis-sion time in network environments. In 3D geometric models, the normal vectors of faces or meshes take a major portion of the data so that the compression of the vectors, which involves the trade off between the distortion of the images and compression ratios, plays a key role in reducing the size of the models. So, raising the compression ratio when the normal vector is compressed and minimizing the visual distortion of shape model's shading after compression are important. According to the recent papers, normal vector compression is useful to heighten com-pression ratio and to improve memory efficiency. But, the study about distortion of shading when the normal vector is compressed is rare relatively. In this paper, new normal vector compression method which is clustering normal vectors and assigning Representative Normal Vector (RNV) to each cluster and using the angular deviation from actual normal vector is proposed. And, using this new method, Visually Undistinguishable Lossy Compression (VULC) algorithm which distortion of shape model's shading by angular deviation of normal vector cannot be identified visually has been developed. And, being applied to the complicated shape models, this algorithm gave a good effectiveness.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.95-104
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• 2022

A TPR-tree is a well-known indexing structure that is developed to answer queries about the current or future time locations of moving objects. For the purpose of space efficiency, the TPR-tree employs the notion of VBR (velocity bounding rectangle)so that a regionalrectangle presents varying positions of a group of moving objects. Since the rectangle computed from a VBR always encloses the possible maximum range of an indexed object group, a search process only has to follow VBR-based rectangles overlapped with a given query range, while searching toward candidate leaf nodes. Although the TPR-tree index shows up its space efficiency, it easily suffers from the problem of dead space that results from fast and constant expansions of VBR-based rectangles. Against this, the TPR-tree index is enforced to update leaf nodes for reducing dead spaces within them. Such an update-prone feature of the TPR-tree becomes more problematic when the tree is saved in flash storage. This is because flash storage has very expensive update costs. To solve this problem, we propose a new Bloom filter based caching scheme that is useful for reducing updates in a flash TPR-tree. Since the proposed scheme can efficiently control the frequency of updates on a leaf node, it can offer good performance for indexing moving objects in modern flash storage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.13-20
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• 2009

Recently there is growing interest in LBS requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based spatial indexes of the spatial main memory DBMS in the main memory, spatial index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMB (relative-sized MBR)compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

• Journal of Korea Spatial Information System Society
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• v.10 no.2
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• pp.1-12
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• 2008

Automatic semiconductor manufacture system generating transaction from 50,000 to 500,000 per a second needs storage management system processing very large data at once. A lot of storage management systems are researched for storing very large data. Existing storage management system is typical DBMS on a disk. It is difficult that the DBMS on a disk processes the 500,000 number of insert transaction per a second. So, the DBMS on main memory appeared to use memory. But it is difficultthat very large data stores into the DBMS on a memory because of limited amount of memory. In this paper we propose storage management system using insert transaction of a block unit that can process insert transaction over 50,000 and store data on low storage cost. A transaction of a block unit can decrease cost for a log and index per each tuple as transforming a transaction of a tuple unit to a block unit. Besides, the proposed system come cost to decompress all block of data because the information of each field be loss. To solve the problems, the proposed system generates the index of each compressed block to prevent reducing speed for searching. The proposed system can store very large data generated in semiconductor system and reduce storage cost.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.663-674
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• 2005

We propose a system aimed at achieving high energy-delay efficiency by using adaptive victim caches. Particularly, we investigate methods to improve the hit rates in the first level of memory hierarchy, which reduces the number of accesses to mort power consuming memory structures such as L2 cache. Victim cache is a memory element for reducing conflict misses in a direct-mapped L1 cache. We present two techniques to fill the victim cache with the blocks that have higher probability to be re-reqeusted by processor. Hit-based victim cache ks tilled with the blocks which were referenced frequently by processor. Replacement-based victim cache is filled with the blocks which were evicted from the sets where block replacements had happened frequently According to our simulations, replacement-based victim cache scheme outperforms the conventional victim cache scheme about $2\%$ on average and refutes the power consumption by up to $8\%$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1914-1924
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• 2014

In this paper, a small-area cell array method of reducing number of SL drivers requiring large layout areas, where the SL drivers supplying programming currents are routed in the row direction in stead of the column direction for eFuse OTP memory IPs having less number of rows than that of columns such as a cell array of four rows by eight columns, and a core circuit are proposed. By adopting the proposed cell array and core circuit, the layout area of designed 32-bit eFuse OTP memory IP is reduced. Also, a V2V ($=2V{\pm}10%$) regulator necessary for RWL driver and BL pull-up load to prevent non-blown eFuse from being blown from the EM phenomenon by a big current is designed. The layout size of the designed 32-bit OTP memory IP having a cell array of four rows by eight columns is 13.4% smaller with $120.1{\mu}m{\times}127.51{\mu}m$ ($=0.01531mm^2$) than that of the conventional design with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$).