• Transactions of Materials Processing
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• v.26 no.6
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• pp.341-347
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• 2017

Flexibly-reconfigurable roll forming (FRRF) is a novel sheet metal forming technology conducive to produce multi-curvature surfaces by controlling strain distribution along longitudinal direction. Reconfigurable rollers could be arranged to implement a kind of punch die set. By utilizing these reconfigurable rollers, desired curved surface can be formed. In FRRF process, three-dimensional surface is formed from two-dimensional curve. Thus, it is difficult to predict the forming result. In this study, a regression analysis was suggested to construct a predictive model for a longitudinal curvature of FRRF process. To facilitate investigation, input parameters affecting the longitudinal curvature of FRRF were determined as maximum compression value, curvature radius in the transverse direction, and initial blank width. Three-factor three-level full factorial experimental design was utilized and 27 experiments using FRRF apparatus were performed to obtain sample data of the regression model. Regression analysis was carried out using experimental results as sample data. The model used for regression analysis was a quadratic nonlinear regression model. Determination factor and root mean square root error were calculated to confirm the conformity of this model. Through goodness of fit test, this regression predictive model was verified.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• Industrial Engineering and Management Systems
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• v.15 no.1
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• pp.11-18
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• 2016

This paper considers a scheduling problem in a flexible job shop with a reconfigurable manufacturing cell. The flexible job shop has both operation and routing flexibilities, which can be represented in the form of a multiple process plan, i.e. each part can be processed through alternative operations, each of which can be processed on alternative machines. The scheduling problem has three decision variables: (a) selecting operation/machine pairs for each part; (b) sequencing of parts to be fed into the reconfigurable manufacturing cell; and (c) sequencing of the parts assigned to each machine. Due to the reconfigurable manufacturing cell's ability of adjusting the capacity, functionality and flexibility to the desired levels, the priority scheduling approach is proposed in which the three decisions are made at the same time by combining operation/machine selection rules, input sequencing rules and part sequencing rules. To show the performances of various rule combinations, simulation experiments were done on various instances generated randomly using the experiences of the manufacturing experts, and the results are reported for the objectives of minimizing makespan, mean flow time and mean tardiness, respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.41-46
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• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

• Nuclear Engineering and Technology
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• v.39 no.1
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• pp.63-74
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• 2007

In this paper, a reconfigurable controller consisting of a normal controller and a standby controller is designed to control the thermoelectric (TE) power in the SP-100 space reactor. The normal controller uses a model predictive control (MPC) method where the future TE power is predicted by using support vector regression. A genetic algorithm that can effectively accomplish multiple objectives is used to optimize the normal controller. The performance of the normal controller depends on the capability of predicting the future TE power. Therefore, if the prediction performance is degraded, the proportional-integral (PI) controller of the standby controller begins to work instead of the normal controller. Performance deterioration is detected by a sequential probability ratio test (SPRT). A lumped parameter simulation model of the SP-100 nuclear space reactor is used to verify the proposed reconfigurable controller. The results of numerical simulations to assess the performance of the proposed controller show that the TE generator power level controlled by the proposed reconfigurable controller could track the target power level effectively, satisfying all control constraints. Furthermore, the normal controller is automatically switched to the standby controller when the performance of the normal controller degrades.

• Transactions of Materials Processing
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• v.17 no.6
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• pp.393-400
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• 2008

Springback is one of the most difficult phenomena to analyze and control in sheet forming. Most of traditional springback control methods rely on experiences of skilled workers in industrial fields. This study focuses on prediction and generation of optimum reconfigurable die surfaces to control shape errors originated by springback. For this purpose, a deformation transfer function(DTF) was combined with finite element analysis of the springback in the 2D sheet forming model of elastic-perfectly plastic materials under the condition without blank holder. The results showed shape errors within 1% of the objective shape, which were comparable with analytically predicted errors. In addition to this theoretical analysis, DTF method was also applied to 2D and 3D sheet forming experiments. The experimental results showed ${\pm}0.5$ mm and ${\pm}1.0$ mm shape error distribution respectively, demonstrating that reconfigurable die surfaces were predicted well by the DTF method. Irrespective of material properties and sheet thickness, the DTF method was applicable not only to FEM simulation but also to 2D and 3D elasto-reconfigurable die forming. Consequently, this study shows that springback can be controlled effectively in the elasto-RDF system by using the DTF method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1061-1064
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• 1998

This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.

• ETRI Journal
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• v.29 no.6
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• pp.832-834
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• 2007

This letter presents a reconfigurable ground-slotted patch antenna using a PIN diode connection in slots to achieve dual-frequency operation. Slots in the ground plane increase the electrical length and thereby reduce antenna size by 53%. By controlling PIN diode conduction, we achieved band hopping while still satisfying the bandwidth requirements for K-PCS and WiBro bands.

• Journal of electromagnetic engineering and science
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• v.15 no.2
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• pp.115-119
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• 2015

This paper proposes a reconfigurable square-patch antenna with polarization diversity. The proposed antenna consists of a square radiating patch and a Y-shaped feed structure with two PIN diodes. The shape of the feed structure can be changed by adjusting the bias states of the two PIN diodes, which helps switch between two orthogonal linear polarizations. The polarization diversity characteristic is validated by the simulated current distribution and the measured radiation pattern.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.