• 항공우주기술
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• 제11권2호
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• pp.73-79
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• 2012

저궤도 위성은 지상과 교신할 수 있는 시간이 매우 제한되어 있으므로 위성에서 생성되는 모든 원격측정 데이터는 대용량 메모리에 저장되었다가 지상교신 시 실시간 데이터와 함께 지상으로 전송된다. 대용량 메모리는 최초 시스템 초기화 과정에서 초기화가 시작되어 각 블록의 상태정보가 생성되고 원격측정데이터를 저장할 수 있는 준비를 한다. 운영 중에 계속적으로 대용량 메모리에 원격측정데이터를 저장하고, 저장된 데이터를 지상으로 전송한다. 그리고 우주환경에서 발생할 수 있는 메모리 오류를 제거하기 위하여 주기적으로 메모리 스크러빙을 수행한다. 본 논문은 저궤도위성 원격측정 데이터 처리를 위한 대용량 메모리 운용방식에 대한 것으로 대용량 메모리 구조, 메모리 초기화 및 메모리 스크러빙 방식, 대용량 메모리를 통한 원격측정데이터 저장 및 전송 방식, 주/부 대용량 메모리 운용 방식에 대해서 기술한다.

• 한국광학회:학술대회논문집
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• 한국광학회 1990년도 제5회 파동 및 레이저 학술발표회 5th Conference on Waves and lasers 논문집 - 한국광학회
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• pp.102-111
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• 1990

In this thesis, an optical bidirectional inner-product associative memory model using liquid crystal television is proposed and analyzed theoretically and realized experimentally. The LCTV is used as a SLM(spatial light modulator), which is more practical than conventional SLMs, to produce image vector in terms of computer and CCD camera. Memory and input vectors are recorded into each LCTV through the video input connectors of it by using the image board. Two multi-focus hololenses are constructed in order to perform optical inner-product process. In forward process, the analog values of inner-products are measured by photodetectors and are converted to digital values which are enable to control the weighting values of the stored vectors by changing the gray levels of the pixels of the LCTV. In backward process, changed stored vectors are used to produce output image vector which is used again for input vector after thresholding. After some iterations, one of the stored vectors is retrieved which is most similar to input vector in other words, has the nearest hamming distance. The experimental results show that the proposed inner-product associative memory model can be realized optically and coincide well with the computer simulation.

• 전기학회논문지
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• 제58권6호
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• 전기의세계
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• 제23권1호
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• pp.73-78
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• 1974

Digital simulation algorithms and program for multimachine dynamic stability have been developed which represent the effects of machines much more complety than have been available previously. Emphasis is given to the savings of the memory spaces required, thus making it possible to use a small computer with limited capacity of core storage (without auxiliary storage). Both d- and q- aris quantities are fully represented, and the speed-governing and voltage-regulating system available are ertensive, thus allowing a very close approximation to any physical system. Facilities for dynamic and nonlinear loads are also included. The computational algorithms and program developed have been shown to be extensive and complete, and are very desirable features minimizing memory spaces for stability calculations. The capabilities have been demonstrated by several case studies for an actual power system of 44 generators, 22 loads and 33 buses. About 13-K words of memory spaces have been required for the case studies on the basis of two words per real variable and a word per integer variable.

• IEIE Transactions on Smart Processing and Computing
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• 제5권4호
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• ETRI Journal
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• 제25권3호
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• pp.179-186
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• 2003

Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32-bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi-resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory-efficient algorithm for the most memory-consuming step (alignment) using a multi-resolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource-constrained environments without significantly degrading accuracy.

• ETRI Journal
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• 제31권6호
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• 정보과학회 논문지
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• 제42권8호
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• pp.972-978
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• 2015

비휘발성 메모리는 바이트 단위 접근과 비휘발성을 지원한다. 이러한 특성들은 비휘발성 메모리를 캐시, 메모리, 디스크와 같은 메모리 계층 구조 가운데 하나의 영역으로 사용을 가능케 한다. 비휘발성 메모리의 흥미로운 특성은 데이터 보존 기간이 실제로는 제한적인 기간을 가지고 있다는 것이다. 게다가 데이터 보존 기간과 쓰기 지연간의 트레이드오프가 존재 한다. 본 논문에서는 이를 활용하여 비휘발성 메모리를 파일 캐시로 사용하는 새로운 관리 기법을 제안한다. 제안하는 기법은 기존의 캐시 관리 기법과는 반대로 짧은 데이터 보존 시간으로 데이터를 저장하고 쓰기 성능을 개선한다. 제안하는 기법은 LRU 대비 평균 접근 지연 시간을 최대 31%, 평균 24.4%로 감소시킴을 보인다.