• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.407-415
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• 1996

This paper introduces two schemes to improve the frame buffer access bandwidth. The first scheme suggests a rasterizer called SBUFRE that has Span Z Buffer and Span Z＆ Color Buffer within a rasterizer. The second scheme suggests a ZDRAM that has Z-value comparator within the DRAM. These schemes are to convert read- modify-write Z buffer compare into single write only operation that improves approximately 50% frame buffer access bandwidth.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1655-1658
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• 2004

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture, called DAVID II, resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that DAVID II achieves almost linear speedup at best case even in sixteen rasterizers.

• Journal of Korea Game Society
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• v.5 no.3
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• pp.39-47
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• 2005

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simulaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that proposed architecture achieves almost linear speedup at best case even in sixteen rasterizer

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.313-315
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• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.298-301
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• 2008

Vector Graphics describes an image with mathematical statements instead of pixel information, Which enables easy scalability without loss in image quality and usually results in a much smaller file size compared with bitmap images. In this paper, we propose Vector Graphics Rasterizer for mobile device with scan-line edge flag algorithm. Proposed Vector Graphics Accelerator was verified with OpenVG 2D Vector image. The estimated performance of proposed Accelerator is 5 frame per second with Tiger image.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.135-143
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• 2004

3D Graphics accelerator is usually composed of two parts, geometry engine and rasterizer. In this paper, VGE(Vector Geometry Engine) which exploits vertex-level parallelism is proposed. In VGE, Common Floating-Point Unit by adding four-FADD, four-FMUL unit and 128-vector register accelerates geometry calculation. In comparison with SH4, Performance result show that the VGE can achieve performance gain over 4.7 times. To evaluate VGE performance, we make simulator to rebuild Simple-Scalar, general purpose processor simulator. In simulator model, we use Viewperf-benchmark.

• Journal of Korea Multimedia Society
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• v.9 no.1
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• pp.41-50
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• 2006

This paper aims to improve the efficiency of a 3D-graphic software engine in a PDA platform and the performance of a rasterizer. There are many problems in implementing a software engine in a mobile platform, due to its relatively weak processing power. Taking the advantages and complementing weaknesses of the depth-sort algorithm and the Z-buffer algorithm, we implemented an adaptive Z-buffer algorithm and proved its performance on several PDA platforms. Our algorithm was evaluated to have midway speed compared with two conventional algorithms. It also removed reversal errors in comparison with the depth-sort algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.1
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• pp.82-97
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• 1999

3차원 그래픽 렌더링은 화면상의 각 화소에 대하여 색깔뿐만 아니라 깊이 정보가지 계산해야 하기 때문에 방대한 계산량과 메모리 접근, 그리고 데이터 전송량을 필요로 하기 때문이다. 따라서 실시간 3차원 그래픽 처리를 위해서 병렬 처리 기법을 도입한다. 그러나 기존 그래픽 가속엔진은 병렬처리 기법으로 영상-병렬성을 이용한 화면 분할 방식을 사용하기 때문에 크게 두 가지 단점이 발생한다. 첫 번재는 화면 영역의 경게에 위치하는 다각형들에 대한 중복계산이고, 두 번째는 낮은 PE(Processing Element) 활용도이다. 본 논문에서는 이러한 문제를 해결하기 위한 방법으로 객체 기반 렌더링(OBR : Object Based Rendering)방식을 바탕으로 하는 그래픽 가속엔진을 제안하였다. OBR 시스템의 목적은 화면 분할 방식의 불필요한 오버헤드를 제거하여 수행 성능을 높이고, 자원을 효율적으로 사용하여 하드웨어 구성비용을 줄이는 것이다. 본 논문에서는 시뮬레이션을 통하여 OBR 시스템이 화면 분할 방식의 대표적인 그래픽 가속기인 PixelFlow와의 성능을 상대적으로 비교하였다. 결론적으로 OBR 시스템은 화면 분할 방식보다 더 적은 하드웨어 자원으로 보다 효율적으로 렌더링을 수해하였다.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.738-740
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• 1998

플래곤-랜더링을 위한 영상합성 구조는 지역 프레임버퍼와 메모리 비용이 큰 문제점을 가진다. 이를 개선하기 위해서 화면-분할 방법과 가상 지역 프레임버퍼 방법이 도입되었으나 이 방법들 역시 상당한 메모리 비용이 요구된다. 본 논문에서는 지역 프레임버퍼 메모리 비용 측면에서 효율적이고, 영상 합성에 필요한 하드웨어를 제거하며, 동시에 영상 합성 시간을 숨길 수 있는 랜더링 시스템과 이에 필요한 병렬 래스터라이져를 설계한다.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.305-316
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• 2006

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.