• Journal of Surface Science and Engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.130.2-130.2
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• 2013

Today, chemical vapor deposition (CVD) of hydrocarbon gases has been demonstrated as an attractive method to synthesize large-area graphene layers. However, special care should be taken to precisely control the resulting graphene layers in CVD due to its sensitivity to various process parameters. Therefore, a facile synthesis to grow graphene layers with high controllability will have great advantages for scalable practical applications. In order to simplify and create efficiency in graphene synthesis, the graphene growth by thermal annealing process has been discussed by several groups. However, the study on growth mechanism and the detailed structural and optoelectronic properties in the resulting graphene films have not been reported yet, which will be of particular interest to explore for the practical application of graphene. In this study, we report the growth of few-layer, large-area graphene films using rapid thermal annealing (RTA) without the use of intentional carbon-containing precursor. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2~3 nm) carbon- and oxygen-containing compounds on a nickel surface and high-temperature annealing of the nickel samples results in the formation of few-layer graphene films with high crystallinity. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time and the resulting films have a limited thickness less than 2 nm even for an extended RTA time. The transferred films have a low sheet resistance of ~380 ${\Omega}/sq$, with ~93% optical transparency. This simple and potentially inexpensive method of synthesizing novel 2-dimensional carbon films offers a wide choice of graphene films for various potential applications.

• Journal of the Korean Ceramic Society
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• v.37 no.5
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• pp.425-431
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• 2000

Cobalt ferrite thin films on Corming glass substrate were fabricated by a sol-gel method. Cobalt ferrite thin films with the grain size of 20-35 nm and thickness of 50nm were obtained. Rapid thermal annealing (RTA) and Annealing processes were adopted for comparison of characteristics of the films. Coercivity values were changed with thermal condition and magnetization values were increased as a function of soaking time. With prolonged soaking time, however, it was decreased because of the diffusion of cations from the glass substrate. The RTA process in preparation of cobalt ferrite thin film was the effective way to prevent and to form a single spinel phase in reduced soaking time. The film heated at 600$^{\circ}C$ for 30 minutes by RTA had coercivity of 2,600 Oe, saturation magnetization 460 emu/㎤, and Mr$.$$\delta$ of 1.43 memu/$\textrm{cm}^2$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.208-212
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• 2004

In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.263-266
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• 2000

Effects of excess Pb(50 mole ％) on the crystallization properties of amorphous PZT thin films on the glass substrates by post-annealing in oxygen ambient were investigated to lower the crystallization temperature of the PZT thin films with a single perovskite phase. The PZT thin films(350nm) were prepared on Pt/Ti/corning glass(1737) substrates. The PZT thin films and bottom electrode were deposited by RF magnetron sputtering. Crystallization properties of PZT thin films were strongly dependent on RTA(Rapid Thermal Annealing) temperature. We were able to obtain a perovskite structure of PZT at 600$^{\circ}C$ for 10min. After thermal treatments were done, electrical properties such as I-V, P-E, and fatigue were measured.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.656-662
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• 2006

We fabricated thermal evaporated 10 nm-$Ni_xCo_{1-x}$ (x=0.2, 0.5 and 0.8) /(poly)Si films to form nanothick cobalt nickel composite silicides by a rapid thermal annealing at $700{\sim}1100^{\circ}C$ for 40 seconds. A field emission scanning electron microscope and a micro-Raman spectrometer were employed for microstructure and silicon residual stress characterization, respectively. We observed self-aligned micro-pinholes on single crystal silicon substrates silicidized at $1100^{\circ}C$. Raman silicon peak shift indicates that the residual tensile strain of $10^{-3}$ in single crystal silicon substrates existed after the silicide process. We propose thermal stress from silicide exothermic reaction and high temperature silicidation annealing may cause the pinholes. Those pinholes are expected to be avoided by lowering the silicidation temperature. Our results imply that we may use our newly proposed composite silicides to induce the appropriate strained layer in silicion substrates.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.276-283
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• 2017

A polysilicon-based metal-semiconductor-metal (MSM) photodetector was fabricated by means of our new methods. Its photoresponse characteristics were analyzed to see if it could be applied to a sensor system. The processes on which this study focused were an alloy-annealing process to form metal-polysilicon contacts, a post-annealing process for better light absorption of as-deposited polysilicon, and a passivation process for lowering defect density in polysilicon. When the alloy annealing was achieved at about $400^{\circ}C$, metal-polysilicon Schottky contacts sustained a stable potential barrier, decreasing the dark current. For better surface morphology of polysilicon, rapid thermal annealing (RTA) or furnace annealing at around $900^{\circ}C$ was suitable as a post-annealing process, because it supplied polysilicon layers with a smoother surface and a proper grain size for photon absorption. For the passivation of defects in polysilicon, hydrogen-ion implantation was chosen, because it is easy to implant hydrogen into the polysilicon. MSM photodetectors based on the suggested processes showed a higher sensitivity for photocurrent detection and a stable Schottky contact barrier to lower the dark current and are therefore applicable to sensor systems.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.73-76
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• 2014

$Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1772-1775
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• 2000

We have fabricated poly-Si TFTs by two-step crystallizaton. Poly-Si films have been prepared by furnace annealing(FA) and rapid thermal annealing(RTA) followed by subsequent the post-annealing, excimer laser annealing. The measured crystallinity of RTA and FA annealed poly-Si film is 77% and 68.5%, respectively. For two-step annealed poly-Si film, the crystallinity has been drastically to 87.7% and 86.3%. The RMS surface roughness from AFM results have been improved from 56.3${\AA}$ to 33.5${\AA}$ after post annealing. The measured transfer characteristics of the two-step annealed poly-Si TFTs have been improved significantly for the both FA-ELA and RTA-ELA. Leakage currents of two-step annealed poly-Si TFTs are lower than that of the devices by FA and RTA. From these results, we can describe the fact that the intra-grain defects has been cured drastically by the post-annealing.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.840-846
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• 1991

In case of the rapid thermal process by halogen lamps, an optical pyrometer is generally used to measure the temperature. It is, however, necessary to measure the temperature by the thermocouple when the process temperature is lower than 700$^{\circ}C$ and the correction of the temperature is required. Contact by the PdAg paste is commonly used out but in this case it is impossible to see the effect of surface states of the substrate, which is critical in the rapid thermal process. In this study, real temperature ramping speed of silicon substrates coveredwith various thin films such as SiO$_2$2, Si$_{3}N_{4}$, dopants, and conductive layers (Ti or Co) was investigated by a mechanical contact of the thermocouple. And the results were compared with the case in which the contact was made by the PdAg paste. Effect of process ambient was also studied. It was found that depending on the surface state, overshoot more than 100$^{\circ}C$ could occur. It was also found that in case of the substrate covered with conductive layers, mechanical contact might render the correct temperature.