• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.481-482
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• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.179-183
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• 2012

The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

• Journal of IKEEE
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• v.21 no.1
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• pp.96-99
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• 2017

In this study the influence of the random dopant fluctuation (RDF) depending on the halo and LDD implantations for the metal-oxide-semiconductor field effect transistor is investigated through the 3D atomistic device simulation. For accuracy in calculation, the kinetic monte carlo method that models individual impurity atoms and defects in the device was applied to the atomistic simulation. It is found that halo implantation has the greater influence on RDF effects than LDD implantation; three-standard deviation of $V_{TH}$ and $I_{ON}$ induced by halo implantation is about 6.45 times and 2.46 times those of LDD implantation. The distributions of $V_{TH}$ and $I_{ON}$ are also displayed in the histograms with normal distribution curves.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.365-375
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• 2014

This paper proposes an abnormal V-shaped-error-free non-blind deconvolution technique featuring an adaptively segmented forward-problem based iterative deconvolution (ASDCN) process. Unlike the algebraic based inverse operations, this eliminates any operations of differential and division by zero to successfully circumvent the issue on the abnormal V-shaped error. This effectiveness has been demonstrated for the first time with applying to a real analysis for the effects of the Random Telegraph Noise (RTN) and/or Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. It has been shown that the proposed ASDCN technique can reduce its relative errors of RTN deconvolution by $10^{13}$ to $10^{15}$ fold, which are good enough for avoiding the abnormal ringing errors in the RTN deconvolution process. This enables to suppress the cdf error of the convolution of the RTN with the RDF (i.e., fail-bit-count error) to $1/10^{10}$ error for the conventional algorithm.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.216-225
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• 2013

This paper discusses the issues regarding an abnormal V-shaped error confronting algebraic-based deconvolution process. Deconvolution was applied to an analysis of the effects of the Random Telegraph Noise (RTN) and Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. This paper proposes a technique to suppress the problematic phenomena in the algebraic-based RDF/RTN deconvolution process. The proposed technique can reduce its relative errors by $10^{10}$ to $10^{16}$ fold, which is a sufficient reduction for avoiding the abnormal ringing errors in the RTN deconvolution process. The proposed algebraic-based analyses allowed the following: (1) detection of the truncating point of the TD-MV distributions by the screening test, and (2) predicting the MV-shift-amount by the assisted circuit schemes needed to avoid the out of specs after shipment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.