• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.187-188
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• 2007

This paper describes a simple and high-performance LDO regulator designed using a $0.18{\mu}m$ CMOS process. It is designed to provide a regulated voltage for on-chip small loads instead of for off-chip heavy loads. Since the load capacitance is very small in this applications, the frequency compensation can be easily achieved without a buffer. The designed LDO drives a load current up to 15mA and dissipates only 12uA quiescent current. The line regulation is and the load regulation is for a 9mA load step. The PSRR at 10kHz is 54dB.

• ETRI Journal
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• 제34권6호
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• 한국통신학회논문지
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• 제22권10호
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• pp.2123-2135
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• 1997

고집적 SRAM을 구성하고 있는 일반적인 메모리 셀을 이용하여 저항성 단락을 MOSFET의 게이트-소오스, 게이트-드레인, 소오스-드레인에 적용시키고, 각 단자에서 발생 가능한 개방 결함을 고려하여 그 영향에 따른 메모리의 자장노드의 전압과 VDD에서의 정전류를 PSPICE 프로그램으로 분석하였다. 해석 결과를 고려하여 메모리의 기능성과 신뢰성을 향상시키기 위해 기능 테스트와 IDDQ 테스트에 동시에 적용할 수 있는 O(N)의 복잡도를 갖는 테스트 알고리즘을 제안하였다. 테스트의 질과 효율을 좀 더 향상시키기 위해 메모리에서 발생되는 고장을 검출하는 BIST 회로와 정전류의 비정상적인 전류의 흐름을 발생시키는 결함을 검출하는 BICS를 설계하였다. 또한 구현한 BIST/BICS 회로는 고장 메모리의 수리를 위해 고장 및 결함의 위치를 검출할 수 있다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• BMB Reports
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• 제43권6호
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• pp.389-399
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• 2010

Fertilization is a complex process comprised of numerous steps. During fertilization, two highly specialized and differentiated cells (sperm and egg) fuse and subsequently trigger the development of an embryo from a quiescent, arrested oocyte. Molecular interactions between the sperm and egg are necessary for regulating the developmental potential of an oocyte, and precise coordination and regulation of gene expression and protein function are critical for proper embryonic development. The nematode Caenorhabditis elegans has emerged as a valuable model system for identifying genes involved in fertilization and the oocyte-to-embryo transition as well as for understanding the molecular mechanisms that govern these processes. In this review, we will address current knowledge of the molecular underpinnings of gamete interactions during fertilization and the oocyte-to-embryo transition in C. elegans. We will also compare our knowledge of these processes in C. elegans to what is known about similar processes in mammalian, specifically mouse, model systems.

• Journal of Astronomy and Space Sciences
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• 제14권2호
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• pp.269-274
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• 1997

Langmuir probe was housed in the sounding rocket to test the probe's performance and to find the environmental parameters at the F layer of the ionosphere. The gold plated cylindrical probe had a length of 14㎝ and a diameter of 0.096 ㎝. The applied voltage to the probe consisted of 0.9 sec fixed positive bias followed by 0.1 sec of down/up sweep. This ensured that the probe swept through the probe's current-voltage characteristic at least once during 1 second quiescent periods enabling the electron temperature to be measured during the undisturbed times of the flight. The experimental results showed good agreement of the temperature distribution with IRI model at the lower F layer. In the upper layer, the experimental temperatures were 100-200K lower than the IRI model's because of the different geomagnetic conditions: averaged conditions were used in IRI model and specific conditions were reflected in the experiment.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.653-656
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• 2005

New charge-recycling structure and driving scheme for TFT-LCD source-driver IC application are proposed. The number of additional switches for the charge recycling is greatly reduced. An experimental prototype 6-bit source driver with five-level seven-phase charge recycling implemented in a $0.35-{\mu}m$ CMOS technology demonstrates that the quiescent current is only 3.1 mA, dynamic power saving is 75 %, and the settling time, which includes the charge-recycling and data driving, is within 25 $25{\mu}s$.

• 전자공학회논문지B
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• 제33B권7호
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• pp.70-79
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• 1996

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

• ETRI Journal
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• 제38권4호
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• pp.654-664
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• 2016

This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권1호
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• pp.47-54
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• 2003

New efficiency enhancement techniques have been devised and implemented to InGaP/GaAs HBT MMIC power amplifiers for W-CDMA mobile terminals applications. Two different types of bias current control circuits that select the efficient quiescent currents in accordance with the required output power levels are proposed for overall power efficiency improvement. A dual chain power amplifier with single matching network composed of two different parallel-connected power amplifier is also introduced. With these efficiency enhancement techniques, the implemented MMIC power amplifiers presents power added efficiency (PAE) more than 14.8 % and adjacent channel leakage ratio(ACLR) lower than -39 dBc at 20 dBm output power and PAE more than 39.4% and ACLR lower than -33 dBc at 28 dBm output power. The average power usage efficiency of the power amplifier is improved by a factor of more than 1.415 with the bias current control circuits and even up to a factor of 3 with the dual chain power amplifier.