• Title/Summary/Keyword: prototype filter

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A Study on QP Method and Two Dimensional FIR Elliptic Filter Design with McClellan Transform (QP 방법과 McClellan 변환을 이용한 2차원 FIR Elliptic 필터 설계에 관한 연구)

  • 김남수;이상준;김남호
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2003.06a
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    • pp.268-271
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    • 2003
  • There are several methods for the design of 2D filter. Notable among them is McClellan transform method. This transform allows us to obtain a high order 2D FIR filter through mapping the 1D frequency points of a 1D prototype FIR filter onto 2D frequency contours. We design 2D filter using this transform. Then we notice for mapping deviation of the 2D filter. In this paper, Quadratic programming (QP) method allows us to obtain coefficients of McClellan transform. Then we compare deviation of QP method with least-squares(LS) method. Elliptic filter is used for comparison. The optimal cutoff frequencies of a 1D filter are obtained directly from the QP method. Also several problem of LS method are solved.

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Interleaved PWM Inverter with Paralleled LCL Filter for Grid Connection (계통 연계를 위한 병렬 LCL 여파기용 Interleaved PWM 인버터)

  • Kim, Hyeon-Dong;Jeon, Seong-Jeub
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.4
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    • pp.275-282
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    • 2022
  • In this study, an inverter system connected to a grid through a paralleled LCL filter is proposed. The system consists of two inverters paralleled and operated with interleaved PWM for powering up and performance improvement. Two LCL filters have two separate filter inductors and one set of filter capacitor and grid inductor in common. The differential mode current circulates through two inverters and two filter inductors. The differential mode current is removed from the filter capacitor and the power grid. Accordingly, performance improvement can be achieved due to the reduced currents in the filter capacitor and the reduced harmonics into a grid. A single-phase prototype has been made and tested, and the proposal has been verified.

An Over Current Protection Scheme for Hybrid Active Power filter

  • Lee Woo-Cheol;Chae Beom-Seok;Hyun Dong-Seok;Lee Taeck-Kie
    • Proceedings of the KIPE Conference
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    • 2001.10a
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    • pp.571-575
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    • 2001
  • A protection scheme for hybrid active power filters, which is combined shunt passive filter and small rated series active filter, is presented and analyzed in this paper. The proposed series active power filter operated as a high impedance 'k($\Omega$)' to the fundamental component when over current occurs in the power distribution system, and three control strategies are proposed in this paper. The first is the method by detecting the fundamental source current through the p-q theory, the second is the method by detecting the fundamental component of load current in Synchronous Reference Frame (SRF) and the third is the method by detecting the input voltage. When the over current occurs in the power distribution system, the proposed scheme protects the series active power filter without additional protection circuits. The validity of proposed protection scheme is investigated through experimental result for the prototype hybrid active power filter system.

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Microstrip Coupled-Line Lowpass Filter with Wide Stopband for RF/Wireless Systems

  • Velidi, Vamsi Krishna;Mandal, Mrinal Kanti;Sanyal, Subrata
    • ETRI Journal
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    • v.31 no.3
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    • pp.324-326
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    • 2009
  • We present the design of a compact microstrip lowpass filter with a wide stopband which is up to ten times the cutoff frequency. The filter is based on a coupled-line configuration and shunt open stubs. The open stubs create additional transmission zeros, which are used to extend the stopband of the filter without any additional components or cascaded units. A prototype lowpass filter with a 3 dB cutoff frequency of 0.428 GHz and a 15 dB stopband extended up to 4.77 GHz is fabricated to validate the theoretical predictions.

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An Efficient Design Method of Linear-Phase Prototype Lowpass Filter for Near-Perfect Reconstruction Pseudo-QMF Banks (근접 완전재생 Pseudo-QMF 뱅크를 위한 선형위상 프로토타입 저역통과 필터의 효율적인 설계 방법)

  • Jeon, Joon-Hyeon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.3C
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    • pp.271-280
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    • 2008
  • M channel near-perfect-reconstruction(NPR) pseudo-QMF banks are a hybrid of conventional pseudo-QMF design and spectral factorization approach where the analysis and synthesis filters are cosine-modulated versions of the prototype-lowpass filter(p-LPF). However, p-LPF H(z) does not have linear-phase symmetry as well as magnitude-distortion optimization since it is obtained by spectral factorization of $2M^{-th}$ band filter $G(z)=z^{-(N-1)}H(z^{-1})H(z)$. A fair amount of attention, therefore, has been focused on the design of filter banks for reducing only alias-cancellation distortion without reconstructed-amplitude distortion. In this paper, we propose a new method for designing linear-phase p-LPF in NPR pseudo-QMF banks, which is based on Maxflat(maximally flat) FIR filters with closed-form transfer function. In addition, p-LPF H(z) is optimized in this approach so that the 2M-channel overall distortion response represented with $G(z)=H^2(z)$ approximately becomes an unit magnitude response. Through several examples of NPR pseudo-QMF banks, it is shown that the peek ripple of the overall magnitude distortion is less than $3.5{\times}10^{-4}\;({\simeq}-70dB)$ and analysis/synthesis filters have the sharp monotone-stopband attenuation exceeding 100 dB.

Equivalent Parallel Capacitance Cancellation of Common Mode Chokes Using Negative Impedance Converter for Common Mode Noise Reduction

  • Dong, Guangdong;Zhang, Fanghua
    • Journal of Power Electronics
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    • v.19 no.5
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    • pp.1326-1335
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    • 2019
  • Common mode (CM) chokes are a crucial part in EMI filters for mitigating the electromagnetic interference (EMI) of switched-mode power supplies (SMPS) and for meeting electromagnetic compatibility standards. However, the parasitic capacitances of a CM choke deteriorate its high frequency filtering performance, which results in increases in the design cycle and cost of EMI filters. Therefore, this paper introduces a negative capacitance generated by a negative impedance converter (NIC) to cancel the influence of equivalent parallel capacitance (EPC). In this paper, based on a CM choke equivalent circuit, the EPCs of CM choke windings are accurately calculated by measuring their impedance. The negative capacitance is designed quantitatively and the EPC cancellation mechanisms are analyzed. The impedance of the CM choke in parallel with negative capacitances is tested and compared with the original CM choke using an impedance analyzer. Moreover, a CL type CM filter is added to a fabricated NIC prototype, and the insertion loss of the prototype is measured to verify the cancellation effect. The prototype is applied to a power converter to test the CM conducted noise. Both small signal and EMI measurement results show that the proposed technique can effectively cancel the EPCs and improve the CM filter's high frequency filtering performance.

On the Design Technique and VLSI Structure for a Multiplierless Quincuncial Interpolation Filter (무곱셈 대각 보간 필터의 설계 및 VLSI 구현에 관한 연구)

  • 최진우;이상욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.29B no.8
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    • pp.54-65
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    • 1992
  • A huge amount of multiplications is required for 2-D filtering on the image data, making it difficult to implement a real-time quincuncial interpolator. In this paper, efficient design technique and VLSI structures for 2-D multipleierless filter are presented. In the filter design, by introducing an efficient scheme for discretizing the frequency response of the prototype filter, it is shown that a significant amount of the computational burden required in the conventional techniques, such as local search, branch and bound techniques, could be saved. In the case of 5$\times$5 filter, it is found that the design technique described in this paper could save about 80% of the computation time, compared to the conventional methods, while providing a comparable performance. For a hardware implementation, two different VLSI structures for 2-D multiplierless filter are also introduced in the paper : One is for block parallel processing and the other for scan-line parallel processing. In both structure, the AP(area-period) figure improves over Wu's structure[4].

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A Study on Design of Active Filters Using Switched Capacitors (Switched Capacitor를 사용한 능동 여파기 설계에 관한 연구)

  • 이문수;김상호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.4 no.1
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    • pp.25-31
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    • 1979
  • All the resitors in the active RC filter networks can be relplaced by the switched capacitors. Therefore, An SC filter circuit can be fully integrated using MOS technology. A switched capacitor is much better than a resistor in temperature and linearity characteristics, and the former can be fabricated on the much smaller area then the latter. In this paper, It is given the generalized disign method of the active SC filter from the active RC filter using Bilinear Z-transformation. By SC filtering Techniques using Bilinear Z-transform, It enalbes us to realize the FDNR and Gyrator filters, which could not be realized in the exsisting designs, and it permits the processing of signals at much higher frequenies that many previous designs do. Experiments show that the response of the SC active filter is similiar to that of its prototype active RC filter.

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A Design of Digital Filter IC Using a Semi-Custom Design Method (Semi-custom 방식을 이용한 디지털 필터의 집적회로 설계)

  • 이광엽;김봉렬;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.2
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    • pp.227-232
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    • 1988
  • A semicustom VLSI design fo digital filters used in TDM/FDM transmultiplexer is described. A filter bank composed of only all-pass digital filter sections are implemented with the polyphase network. The use of all-pass filters as basic building blocks is shown to provide a trans-multiplexer structure that has low computational requirements, low quantization noise, and high modularity. The silicon compiler system is used to reduce the design time and to increase the credibility of designed filters. As a prototype, 1st and 2nd order all pass filter are designed, using CMOS N-well double metal technology. The chip sizes of first order filter and the second order filter are 2652 x 533\ulcorner\ulcorner 5334x4300\ulcorner\ulcorner respectively.

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A Three-Phase Parallel Active Power Filter Operating with PCC Voltage Compensation by Controlling Reactive Power (무효전력 제어에 의한 PCC전압 보상을 갖는 삼상 병렬형 능동전력필터)

  • Lee, U-Cheol;Hyeon, Dong-Seok;Lee, Taek-Gi
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.49 no.3
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    • pp.211-218
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    • 2000
  • The performance and dynamic characteristics of three-phase active power filter with PCC voltage compensation is presented and analyzed in this paper. The characteristics of parallel active filter are discussed when they are applied to nonlinear loads with current source and voltage source type, the characteristics of voltage compensator and comparison of two functions are discussed. The proposed scheme in this paper employs a PWM voltage-source inverter and has two operation modes. First, it operates as a conventional active filter with reactive power compensation while PCC voltage is in a certain range. Second, is operates as a voltage compensator while PCC voltage is out of range. Finally, the validity of this scheme is investigated through analysis of simulation and experimental results for a prototype active power filter system rated at 10KVA.

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