• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.34-42
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• 1981

A 512-bit Task Programmable ROM has been designed and fabricated using PMOS technology. The content of the memory was written through the gate pattern during the fabrication process, and was checked by displaying the output of the chip on an oscilloscope with 512(32$\times$16) matrix points. The operation of the chip was surcessful with operating voltage from -6V to -l2V, The power consumption and propagation delay time have been measured to be 3mW and 13 $\mu$sec, respectively at -6 Volt. The power consunption increased to 27mW and propagation delay time decreased to 3$\mu$sec at -12V. The output of the chip was capable of driving the input of a TTL gate directly and retained a high impedence state when the chip solect function disabled the output.

• Journal of Bio-Environment Control
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• v.4 no.2
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• pp.203-210
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• 1995

Using the programmable logic controller (PLC), a kind of microcomputer, a facility to control EC and pH automatically in nutriculture of tomato was developed. A program for the automatic control of nutriculture was written in ladder diagram language. EC and pH levels of nutrition solution could be maintained at 1.70-1.72 and 6.1-6.5, respectively, during the entire growing period. Better fruits and higher yield were obtained in automatic control plot than in the control plot. Inorganic elements in plant were higher in the former than in the latter.

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1192-1205
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• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• Journal of the Korea Computer Graphics Society
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• v.16 no.4
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• pp.11-16
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• 2010

We present an efficient algorithm for rendering sweep surfaces using programmable graphics hardware. A sweep surface can be represented by a cross-section curve undergoing a spline motion. This representation has a simple matrix-vector multiplication structure that can easily be adapted to programmable graphics hardware. The data for the motion and cross-section curves are stored in texture memory. The vertex processor considers a pair of surface parameters as a vertex and evaluates its coordinates and normal vector with a single matrix multiplication. Using the GPU in this way is between 10 and 40 times as fast as CPU-based rendering.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1022-1026
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• 2007

We have demonstrated new functionalities of Ag doped chalcogenide glasses based on their capabilities as solid electrolytes. Formation of such amorphous systems by the introduction of silver via photo-induced diffusion in thin chalcogenide films is considered. The influence of silver on the properties of the newly formed materials is regarded in terms of diffusion kinetics and Ag saturation is related to the composition of the hosting material. Silver saturated chalcogenide glasses have been used in the formation of solid electrolyte which is the active medium in programmable metallization cell (PMC) devices. In this paper, we investigated electrical and optical properties of Ag-doped chalcogenide thin film on changed thickness of Ag and chalcogenide thin films, which is concerned at Ag-doping effect of PMC cell. As a result, when thickness of Ag and chalcogenide thin film was 30 nm and 50 nm respectively, device have excellent characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.05
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• pp.260-265
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• 1996

The purpose of this study was to implemented a general purpose programmable nerve stimulator system as a research tool for studying psychophysiological performance associated with various stimulation waveform. This system is composed of hardware and software, the former are the personal computer(180586) and control unit(one-chip microprocessor, D/A converter, digital output), the latter are programmed in VISUAL BASIC and ASSEMBLY Which are programmed for the programmable nerve stimuli pattern editor and communication interface, waveform preprocessing, and stimuli generator. The control unit which is entrolled by the personal computer is capable of delivering the programmable nerve stimuli waveform. This system has research potential for determining the effect of various neuromuscular blockade in alternated physiological stat is.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.35-41
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• 2014

This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.