• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.4
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• pp.43-49
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• 2012

Recently computer technologies have been actively applied for our daily life such as image processing, wireless communications, and programmable robots, etc. In the paper, we develop a new programmable robot cushion that detects a user's posture, and gives feedback to the user by integrating and converging these technologies. Furthermore, we analyze the effects of IT convergence programmable robots for undergraduate students in the major of computer science and engineering to define and solve the problems creatively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.1
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• pp.87-96
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• 2002

This paper proposes an efficient decimation filter structure in programmable down converter for software radio. The decimation filter consists of the cascaded integrator-comb(CIC) filter, a compensation filter for CIC, cascaded comb and modified halfband filters, and programmable FIR filter. Since the compensation filter is used in CIC, the passband drooping is compensated and stopband attenuation is improved. Therefor the more decimation can be implemented in CIC filter. The compensation filter in CIC reduced the computational complexity of other decimation filters and the coefficients of PFIR, thereby achieving a significant hardware reduction over existing approaches. We can reduce the multiply operator by 20% in hardware and operation by 50% as compared with PDC of Harris.

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.253-261
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• 2008

Programmable metallizaton cell (PMC) memory device has been known as one of the next generation non-volatile memory devices, because it includes non-volatility, high speed and high ON/OFF resistance ratio. This paper reviews the operation principle of the device. Besides, the recent research results of professor Kozicki who firstly invented the device and investigated it for the memory applications, NEC corporation which studied it for the FPGA (field programmable gate array) switch applications, ETRI and chungnam national university which examined Te-based devices are introduced.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.33-38
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• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.767-769
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• 2002

A novel RE configurable device composed by bare-chip, bumps and board are proposed. We call this "Field-Programmable RF Gate Array (FPRA)," This device, a kind of programmable system packages, has a potential to be applied to wireless communication terminals such as software-defined radio.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.169-174
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• 1986

This thesis investigates the scanning time ; one of the most important performance index of Programmable Controller(PC). The multiprocessor architecture of the large PC considered in this thesis are classified as architecture 1 and architecture 2 by the bus control methods. The queuing model of each architecture is developed. Form the analysis it is observed that in the case of the number of processors less than 3 the best architecture of the large PC is the architecture 2 and in the case of the number of processors greater than 2 the best architecture of the large PC is the architecture 1.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.917-920
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• 1993

Various forms of hardware alternatives exist for the implementation of fuzzy logic controllers. In this paper, we describe a systematic framework for realizing fuzzy heuristics on programmable-logic-devices. Our approach is suitable for the automated development of fuzzy logic controllers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.29-38
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• 1997

As the trend of the automation is increasing, the usage of the programmable automation equipments like programmable controller(PC), numerical controller(NC), distributed control systems(DCS) and robot controller is greatly expanding in the area of the industrial equipments. But the development of the programing language for the programmable automatic equipment is rarely accomplished. In this paper, we propose design and implementation technique of the real-time mechanism control language by adding time constraint constructs and timing analysis constructs ot conditional statement and iteration statement of a programming language. Moreover, we made it possible to predict plausibility of time constraint constructs of a real time application program at compilation time and developing execution time analysiss technique.