• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.500-505
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25$\mu\textrm{m}$ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65$\mu\textrm{m}$ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of ${\pm}$10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5${\mu}\textrm{s}$, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.73-83
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• 2004

With increasing numbers of vehicles on restricted roads, It happens that we have much wasted time and decreased average car speed. This paper proposes a new concept of coordinating green time which controls 10 traffic intersection systems. For instance, if we have a baseball game at 8 pm today, traffic volume toward the baseball game at 8 pm today, franc volume toward the baseball game will be increased 1 hour or 1 hour and 30 minutes before the baseball game. At that time we can not predict optimal green time Even though there have smart electro-sensitive traffic light system. Therefore, in this paper to improve average vehicle speed and reduce average vehicle waiting time, we created optimal green time using fuzzy rules md neural network as a preprocessing. Also, we developed an Intelligent PLC(Programmable Logic Controller) for real time traffic forecasting as a postprocesing about unexpectable conditions. Computer simulation results proved reducing average vehicle waiting time which proposed coordinating green time better than electro-sensitive franc light system does not consider coordinating green time.

• Molecules and Cells
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• v.40 no.11
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• pp.823-827
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• 2017

Genome editing using programmable nucleases such as CRISPR/Cas9 or Cpf1 has emerged as powerful tools for gene knock-out or knock-in in various organisms. While most genetic diseases are caused by point mutations, these genome-editing approaches are inefficient in inducing single-nucleotide substitutions. Recently, Cas9-linked cytidine deaminases, named base editors (BEs), have been shown to convert cytidine to uridine efficiently, leading to targeted single-base pair substitutions in human cells and organisms. Here, we first report on the generation of Xenopus laevis mutants with targeted single-base pair substitutions using this RNA-guided programmable deaminase. Injection of base editor 3 (BE3) ribonucleoprotein targeting the tyrosinase (tyr) gene in early embryos can induce site-specific base conversions with the rates of up to 20.5%, resulting in oculocutaneous albinism phenotypes without off-target mutations. We further test this base-editing system by targeting the tp53 gene with the result that the expected single-base pair substitutions are observed at the target site. Collectively, these data establish that the programmable deaminases are efficient tools for creating targeted point mutations for human disease modeling in Xenopus.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.349-351
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• 2013

This research paper presents a low-power programmable gain amplifier (PGA) to facilitate signal processing of the detection of defects in steel plates. This circuit is able to adjust a gain in the range of 6 to 60dB in 7 steps using different signal types for various defects from hall sensors. The gain of PGA is designed by operating on-resistors of switches and passive components. The proposed PGA ($0.18{\mu}m$ CMOS process with 1.8 supply voltage) showed excellent gain error of less than -0.2dB, and low power consumption of 0.47mW.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.20 no.3
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• pp.118-124
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• 2019

Recently, the industrial field has been changed to the smart factory system based on information and communication technology (ICT) in order to improve productivity, quality and customer satisfaction. The most important machine to realize the smart factory is the AGV(automatic guided vehicle) and the adoption of AGV is increasing. Generally, AGV is developed using general purpose PLC(Programmable Logic controller), but the price of AGV is expensive and its volume is large. On the other hand, the industrial field due to space constraints in the workplace is required the low cost AGV which can be minimization, expansion of function, and easily reconfiguration. Therefore, in order to solve these problems, this study is proposed a design method of AGV controller with built-in PLC, and evaluated its performance. In the results of the experimentation, it showed good performance (speed control error = 0.021[m/s], posture control error=2.1[mm]) for the speed and posture control. In this way, when applying the proposed AGV controller in this study to the industrial filed, it is possible to reduce the size and reconfigure at low cost.