• Journal of information and communication convergence engineering
• /
• v.3 no.3
• /
• pp.142-145
• /
• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Journal of information and communication convergence engineering
• /
• v.15 no.3
• /
• pp.151-159
• /
• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1262_1263
• /
• 2009

Programmable Metallization Cell (PMC) is a memory device based on the electrolytical characteristic of chalcogenide materials. In this study, we investigate the nature of thin films formed by photo doping of Ag ions into chalcogenide materials for use in solid electrolyte of programmable metallization cell devices. We were able to do more economical approach by using copper which play an electrolyte ions role. The results imply that a Ag-rich phase separates owing to the reaction of Ag with free atoms from chalcogenide materials.

• International Journal of Contents
• /
• v.11 no.4
• /
• pp.70-76
• /
• 2015

The development of technology provides and increases security as well as convenience for humans. The development of new technology directly affects the standard of life thanks to smart home automatic control systems. This paper describes a door control, automatic curtain, home security (CCTV, fire, gas, safe, etc.), home control (energy, light, ventilation, etc.) and web-based smart home automatic controller. It also describes the use of ARM (Advanced RISC Machines) for automatic control of home equipment, a Multi-Axes Servo Controller using FPGA (Field Programmable Gate Array) and PLC (programmable logic controller). Additionally, it describes the development of a HTML editor using web auto control software. The tab loading time (7 seconds) is faster when using ARM-based web browser software instead of Chrome and Firefox is used because the browser has a small memory footprint (300M). This system is realized by web auto controller language which controls and uses PLCs that are easier than existing devices. This smart home automatic control technology can control smart home equipment anywhere and anytime and provides a remote interface through mobile equipment.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2003.11b
• /
• pp.557-560
• /
• 2003

In this paper, we developed an editor and running engine for the SoftPLC. LD is the most popular standard IEC 1131-3 PLC language in Korea and used over 90% among the 5 PLC languages. In this paper, we have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user is converted to IL, which is one of intermediate codes, and IL is converted to the standard C code which can be used in a commercial editor such as visual C++. In ISPLC, the detection of logical error in high level programming(C) is more efficient than PLC programming itself. ISPLC provide easy programming platform to such beginner as well as professionals. The study of code conversion of LD-> U->C is firstly tried in the world as well as KOREA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.05a
• /
• pp.437-438
• /
• 2018

본 논문은 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 프로그램 가능한 디지털 필터를 제안한다. 이러한 필터는 Altera사의 FPGA(Field Programmable Gate Array)인 cycloneII EP2C70F89618를 이용하여 구현하였다. 데이터 신호에 포함된 잡음 제거 알고리즘을 바탕으로 한 출력 영상 신호 결과로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 잡음이 제거된 출력 영상 특성을 보임을 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.40 no.8
• /
• pp.836-844
• /
• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.288-290
• /
• 2006

This paper presents the real-time water tank wireless control in a ship using duplex RF modules and PLC(Programmable logic Controller). The purpose of this paper is developing HMI(Human Machine Interface) for automation equipments. The system can low a cost because long wires are no more used. Analog signals of the water gauge and flow meter are changed to discrete signals by the micro-processor. The PLC checks the volume of water and runs On or Off of the valve and pump. Duplex RF modules send and receive data between the water tank and control room. Everywhere the Internet is used, operators are able to check the status of the system by the web-server.

• 제어로봇시스템학회:학술대회논문집
• /
• 1987.10a
• /
• pp.863-869
• /
• 1987

INFOBUS, which has been designed as a system bus of a multiprocessor system, will be introduced. And the concepts of the multiple transfer and ORed write transfer will be described. These concepts make INFOBUS to be well suited for use as the system bus of the multiprocessor based programmable controller(MBPC). In addition, the mean data transfer time through INFOBUS, which is one of the most significant performance of a bus, will be obtained by analysis and simulation. Next, MBPC which uses INFOBUS as its system bus will be introduced, and some basic characteristics of MBPC will be described. The construction of exact model for MBPC will be given and simulated using SDL/SIM package. The reference system of our model will be briefly described also. Some results from the simulation will be given and validated.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.2
• /
• pp.25-30
• /
• 1985

This paper proposes an algorithm to simplify Boolean functions into near minimal sum-of-products for Programmable Logic Arrays. In contrast to the conventional procedures, where the execution time depends on the number of variables, the execution time by this procedure depends on the degree of consensus of base minterms. Thus as the number of variables is increased, the difference of CPU time becomes larger using this new Procedure than using other procedures and consequently the executable range of input function increasing. The algorithm has been implemented on CYEER 170-740 and it's results were compared with those using Arvalo's algorithm.