• 제목/요약/키워드: processing architecture

검색결과 2,766건 처리시간 0.032초

An Effective Architecture for Reliable Communications in VDTN

  • Morales, Mildred Madai Caballeros;Hong, Choong Seon
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2010년도 추계학술발표대회
    • /
    • pp.1046-1049
    • /
    • 2010
  • Custody transfer method is often managed by the general architecture of Delay Tolerant Network (DTN) to provide reliability in the communications through storage and forward paradigm, but can be inefficient when the acknowledgment messages are lost, or the network becomes congested. In this paper we describe a new architecture that is particularly efficient for the custody transfer method. Because, it provides an additional control of acknowledgment messages, consolidate knowledge and services, using the advantage of the cross-over architectures and distribution control through local and global services.

PSTR 기반의 Fault Tolerant Architecture (Fault Tolerant Architecture based on PSTR in Flight Control System)

  • 김준영;이근수;김두현
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2009년도 추계학술발표대회
    • /
    • pp.79-80
    • /
    • 2009
  • 최근 UAV(Unmanned Aerial Vehicle)의 OFP(Operation Flight Program)에 대한 많은 연구가 진행되고 있다. UAV의 OFP는 경성 소프트웨어 일종으로 Time deadline과 수많은 요인으로 인한 Fault에 대하여 소프트웨어의 높은 신뢰성이 요구가 된다. 본 논문에서는 UAV의 OFP에 대하여 STR(Primary-Shadow TMO replication)기반의 fault tolerant Architecture에 대하여 제안을 한다.

Towards a Next Generation of Data Capture Architecture of Honeynets

  • Yong-Kyung Oh;Inhyuk Kim;Young Ik Eom
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2008년도 추계학술발표대회
    • /
    • pp.1469-1472
    • /
    • 2008
  • Honeynets have become one of essential tools in system and network security. As the importance of security has increased over the years, many researchers try to improve the overall Honeynet architecture. Due to their efforts, the Honeynets have evolved up to the third generation. However, the GenIII architecture has some limitations. In this paper, we address some of the limitations and provide solutions by redesigning the framework of data capture of Honeynets.

An Efficient Public Key Based Security Architecture for Wireless Sensor Networks

  • Haque, Mokammel;Pathan, Al-Sakib Khan;Hong, Choong-Seon
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2007년도 춘계학술발표대회
    • /
    • pp.1098-1099
    • /
    • 2007
  • In this paper, we propose a public key based security architecture for Wireless Sensor Networks (WSNs). The basic architecture comprises of two schemes; a key handshaking scheme based on simple linear operations for fast computation and an identity based cryptosystem which does not require any certificate authority. Our analysis shows that, the combined scheme ensures a good level of security and is very much suitable for the energy constrained trend of wireless sensor network.

안전필수 시스템을 위한 시간기반 MDA 아키텍처 모델링 (Time-Based MDA Architecture Modeling for Safety-Critical Systems)

  • 임유진;최은미
    • 정보화연구
    • /
    • 제9권4호
    • /
    • pp.443-453
    • /
    • 2012
  • 다양한 분야의 시스템들은 시스템 오류에 인한 피해의 최소화를 목적으로 안전필수 특성을 가지도록 요구된다. 본 논문에서, 안전필수 시스템으로 많이 연구되는 사이버물리시스템이 그 특성을 가지기위해 고려해야하는 이슈와 주요 요소인 시간을 기반으로 모델 지향 아키텍처에 대하여 논의한다. 메타모델링 접근 방식으로 마감시간, 전환상태와 기준치에 연결하여 시간 기반 아키텍처를 제시하고, 이를 모델지향 아키텍처를 이용하여 설계한다. 메타모델로부터 생성된 안전처리 모델과 함께 오류처리 컴포넌트를 사용하여 사이버 물리 시스템 및 시간기반 도메인에 적용 가능한 안전필수 아키텍처를 제시한다. 그리고 안전필수 시스템 설계 시 기본적 안전처리 상태, 다중적 상태, 복합적 상태를 통하여 세부적인 모델과 그 사례를 나타내었다.

Extended CEP Model for Effective Enterprise Systems Service Monitoring

  • Kum, Deuk Kyu
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • 제14권2호
    • /
    • pp.807-825
    • /
    • 2020
  • In recent years, business environments have become more complex; therefore, enterprises must be capable of responding flexibly and agilely. For these purposes, effective enterprise systems service monitoring and early decision making based on the same, emerge as core competency of the enterprise. In addition, enterprise system techniques that filter meaningful data are needed to event processing. However, the existing study related with this is nothing but discovering of service faults by monitoring depending upon API of BPEL engine or middleware, or is nothing but processing of simple events based on low-level events. Accordingly, there would be limitations to provide useful business information. In this study, we present an extended event processing model that enables delivery of more valuable and useful business information through situation detection. Primarily, the event processing architecture in an enterprise system is proposed as a definite approach, and then define an event meta-model suitable for the proposed architecture. Based on the defined model, we propose the syntax and semantics of the elements that make up the event processing language include various and progressive event operators, the rules, complex event pattern, etc. In addition, an event context mechanism is proposed to analyze more delicate events. Finally, the effectiveness and applicability of proposed approach is presented through a case study.

An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection

  • Kim, Dong-Kyun;Jung, Jun-Hee;Nguyen, Thuy Tuong;Kim, Dai-Jin;Kim, Mun-Sang;Kwon, Key-Ho;Jeon, Jae-Wook
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제12권2호
    • /
    • pp.150-161
    • /
    • 2012
  • Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image.

실시간 내장형 응용을 위한 2차원 웨이브렛 변환 프로세서 (2D DWT Processor for Real-time Embedded Applications)

  • 정갑천;박성모
    • 전자공학회논문지CI
    • /
    • 제40권2호
    • /
    • pp.17-25
    • /
    • 2003
  • 본 논문에서는 상태 변수 표현 방법에 따른 알고리즘 분할을 통해 2차원 웨이브렛 변환 연산을 실시간으로 처리할 수 있는 프로세서 구조를 제안하였다. 제안된 프로세서 구조는 영상입력에 대하여 행, 열 방향을 동시에 고려하여 데이터 플로우 방식으로 처리함으로써 중간적인 결과의 메모리 저장 및 읽기에 소요되는 전달 지연 시간을 감소할 수 있어 실시간 처리에 적합한 VLSI 구조이다. 필터의 길이를 K라할 때 프로세서는 내부에 4개의 곱셈기, 4개의 덧셈기 및 NK-N 크기의 메모리를 가지는 등의 하드웨어 복잡도가 낮아 웹 카메라 서버와 같은 내장형의 응용에 매우 적합한 구조이고, 쉽게 어레이 구조로 확장할 수 있어 고성능을 요구하는 다양한 영상 처리 응용에도 사용 가능하다.

완전탐색 블럭정합 알고리즘을 위한 일차원 시스톨릭 어레이의 구조 (An Architecture of One-Dimensional Systolic Array for Full-Search Block Matching Algorithm)

  • 이수진;우종호
    • 전자공학회논문지SC
    • /
    • 제39권5호
    • /
    • pp.34-42
    • /
    • 2002
  • 본 논문에서는 움직임 추정을 위한 블럭정합 알고리즘의 고속 처리를 위한 VLSI 어레이의 구조를 설계하였다. 완전탐색 블럭정합 알고리즘의 데이터 의존관계로부터 일차원 시스톨릭 어레이를 유도했다. 제안된 일차원 시스톨릭 어레이에 입력된 데이터와 제어신호는 인접한 처리요소를 통해서 전달되어 재사용된다. 따라서 제안된 시스톨릭 어레이는 시간 및 공간적 지역성을 만족한다. 데이터와 제어신호의 입출력 핀은 일차원 어레이의 시작과 끝의 처리요소에만 존재한다. 이 구조는 입력포트의 수가 적으며, 모듈러 확장성을 갖는다. 기준블럭과 최대탐색거리가 확장된 경우에 제안된 어레이를 연결하여 움직임 추정기를 구성할 수 있다.

Parallel Processing of the Fuzzy Fingerprint Vault based on Geometric Hashing

  • Chae, Seung-Hoon;Lim, Sung-Jin;Bae, Sang-Hyun;Chung, Yong-Wha;Pan, Sung-Bum
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • 제4권6호
    • /
    • pp.1294-1310
    • /
    • 2010
  • User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.