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An Architecture of One-Dimensional Systolic Array for Full-Search Block Matching Algorithm  

Lee, Su-Jin (Division of Electronics Computer and Communication Eng., Pukyong National University)
Woo, Chong-Ho (Division of Electronics Computer and Communication Eng., Pukyong National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.5, 2002 , pp. 34-42 More about this Journal
Abstract
In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.
Keywords
움직임추정;블럭정합;로컬패스;시스톨릭 어레이;
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