KSII Transactions on Internet and Information Systems (TIIS)

Korean Society for Internet Information (한국인터넷정보학회)
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Parallel Processing of the Fuzzy Fingerprint Vault based on Geometric Hashing

  • Chae, Seung-Hoon (Dept. of Information and Communication Engineering, Chosun Univ.) ;
  • Lim, Sung-Jin (Dept. of Information and Communication Engineering, Chosun Univ.) ;
  • Bae, Sang-Hyun (Dept. of Computer Science and Statistics, Chosun Univ.) ;
  • Chung, Yong-Wha (Dept. of Computer and Information Science, Korea Univ.) ;
  • Pan, Sung-Bum (Dept. of Information and Communication Engineering, Chosun Univ)
  • Received : 2010.05.24
  • Accepted : 2010.10.07
  • Published : 2010.12.23
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Abstract

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

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References

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