• Journal of Institute of Control, Robotics and Systems
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• v.20 no.7
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• pp.767-773
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• 2014

The carrier-to-noise power ratio is a key parameter for determining the reliability of PVT (Position, Velocity, and Time) solutions which are obtained by a GNSS (Global Navigation Satellite System) receiver. It is also used for locking a tracking loop, deciding the re-acquisition process, and processing advanced navigation in the receiver subsystem. The representative carrier-to-noise power ratio estimation schemes are the narrowband-wideband power ratio method (NW), the MM (Moment Method), and Beaulieu's method (BL). The NW scheme is the most classical one for commercial GNSS receivers. It is often used as an authoritative benchmark for assessing carrier-to-noise power estimation schemes. The MM scheme is the least biased solution among them, and the BL scheme is a simpler scheme than the MM scheme. This paper focuses on the less biased estimation with low complexity when the residual phase noise remains, then proposes a novel carrier-to-noise power ratio estimation scheme with low complexity for GNSS receivers. The asymptotic bias of the proposed scheme is derived and compared with others, and the simulation results demonstrate that the complexity of the proposed scheme is lowest among them, while the estimation performance of the proposed scheme is similar to those of the BL and MM schemes in normal and high gained reception environments.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• Analyses & Alternatives
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• v.7 no.2
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• pp.35-77
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• 2023

This study aims to solve the entangled loop between demographic transition (DT) and economic growth by analyzing cross-country data. We undertake a national-level group analysis to verify the compressed transition of demographic variables over time. Assuming that the LA (latecomer advantage) on DT over time exists, we verify that the DT of the latecomer is compressed by providing a formal proof of LA on DT over income. As a DT has the double-kinked functions of income, we check them in multiple aspects: early maturation, leftward threshold, and steeper descent under a contour map and econometric methods. We find that the developing countries (the latecomer) have speedy DT (CDT, compressed DT) as well as speedy income such that DT of the latecomers starts at lower levels of income, lasts for a shorter period, and finishes at the earlier stage of economic development compared to that of developed countries (the early mover). To check the balance of DT, we classify countries into four groups of DT---balanced, slow, unilateral, and rapid transition countries. We identify that the main causes of rapid transition are due to the strong family planning programs of the government. Finally, we check the effect of latecomer's CDT on economic growth inversely: we undertake the simulation of the CDT effect on economic growth and the aging process for the latecomer. A worrying result is that the CDT of the latecomer shows a sharp upturn of the working-age population, followed by a sharp downturn in a short period. Compared to early-mover countries, the latecomer countries cannot buy more time to accommodate the workable population for the period of demographic bonus and prepare their aging societies for demographic onus. Thus, we conclude that CDT is not necessarily advantageous to developing countries. These outcomes of the latecomer's CDT can be re-interpreted as follows. Developing countries need power sources to pump up economic development, such as the following production factors: labor, physical and financial capital, and economic systems. As for labor, the properties of early maturation and leftward thresholds on DTs of the latecomer mean that demographic movement occurs at an unusually early stage of economic development; this is similar to a plane that leaks fuel before or just before take-off, with the result that it no longer flies higher or farther. What is worse, the property of steeper descent represents the falling speed of a plane so that it cannot be sustained at higher levels, and then plummets to all-time lows.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.6
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• pp.116-126
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• 2021

Ground Component Command (GCC) has been developing operational planning and execution systems to implement "Decisive Integrated Operations", which is the concept of ground operations execution, and achieved remarkable results. In particular, "Simultaneous Offense-Defense Integrated Operations" is developed mainly to neutralize enemies in deep areas and develop favorable conditions for the allies early by simultaneously attacking and defending from the beginning of the war. On the other hand, it is limited to providing scientific and reasonable support for the commander's decision-making process because analyzing the effects of the deep operation with existing M&S systems is impossible. This study developed a model for analyzing the effects of deep operations that can be used in the KJCCS. Previous research was conducted on the effects of surveillance, physical strike, and non-physical strike, which are components of deep operations to find the characteristics and limitations and suggest a research direction. A methodology for analyzing the effects of deep operations reflecting the interactions of components using data was then developed by the GCC, and input data for each field was calculated through combat experiments and a literature review. Finally, the Deep operations Effect CAlculating Model(DECAM) was developed and distributed to the GCC and Corps battle staff during the ROK-US Combined Exercise. Through this study, the effectiveness of the methodology and the developed model were confirmed and contribute to the development of the GCC and Corps' abilities to perform deep operations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.