• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.52-58
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• 2009

If a moving target has a linear characteristics, the Kalman filter can estimate relatively accurate the location of a target, but this performance depends on how the dynamic status characteristics of the target is accurately modeled. In many practical problems of tracking a maneuvering target, a simple kinematic model can fairly accurately describe the target dynamics for a wide class of maneuvers. However, since the target can exhibit a wide range of dynamic characteristics, no fixed SKF(Simple Kalman filter) can be matched to estimate, to the required accuracy, the states of the target for every specific maneuver. In this paper, a new AKF(Active Kalman filter) is proposed to solve this problem The process noise covariance level of the Kalman filter is adjusted at each time step according to the study result which uses the neural network algorithm. It is demonstrated by means of a computer simulation that the tracking capability of the proposed AKF(Active Kalman filter) is better than that of the SKF(Simple Kalman Filter).

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.18-23
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• 2012

In this paper, a potable device application for DC-DC converter was designed for voltage protection circuit. Voltage protection circuit to offer the under voltage lock out and over voltage protection consists of a comparator and bais circuits were implemented using. XFAB 1um CMOS process, SPICE simulations was confirmed through the characteristics. Simulation results, under voltage lock out input voltage is 4.8 V higher when the turn-on and, 4.2 V less when turn-off. When the input voltage is low voltage is applied can be used to prevent malfunction of the circuit. Over voltage protection is 3.8 V reference voltage when the output voltage caused by blocking circuit prevents device destruction can be used to improve the stability and reliability. The virtual control circuits of the DC-DC converter connected. According to the results of the abnormal voltage, voltage protection circuit behavior was confirmed. The proposed voltage protection circuit of the DC-DC converter cell is useful are considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.619-628
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• 2019

In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

• Journal of the Korean Society of Safety
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• v.32 no.2
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• pp.34-37
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• 2017

In recent emerging industry, Display field becomes bigger and bigger, and also semiconductor technology becomes high density integration. In Flat Panel Display, there is an issue that electrostatic phenomenon results in fine dust adsorption as electrostatic capacity increases due to bigger size. Destruction of high integrated circuit and pattern deterioration occur in semiconductor and this causes the problem of weakening of thermal resistance. In order to solve this sort of electrostatic failure in this process, Soft X-ray ionizer is mainly used. Soft X-ray Ionizer does not only generate electrical noise and minute particle but also is efficient to remove electrostatic as it has a wide range of ionization. X-ray Generating efficiency has an effect on soft X-ray Ionizer affects neutralizing performance. There exist variable factors such as type of anode, thickness, tube voltage etc., and it takes a lot of time and financial resource to find optimal performance by manufacturing with actual X-ray tube source. MCNPX (Monte Carlo N-Particle Extended) is used for simulation to solve this kind of problem, and optimum efficiency of X-ray generation is anticipated. In this study, X-ray generation efficiency was measured according to target material thickness using MCNPX under the conditions that tube voltage is 5 keV, 10 keV, 15 keV and the target Material is Tungsten(W), Gold(Au), Silver(Ag). At the result, Gold(Au) shows optimum efficiency. In Tube voltage 5 keV, optimal target thickness is $0.05{\mu}m$ and Largest energy of Light flux appears $2.22{\times}10^8$ x-ray flux. In Tube voltage 10 keV, optimal target Thickness is $0.18{\mu}m$ and Largest energy of Light flux appears $1.97{\times}10^9$ x-ray flux. In Tube voltage 15 keV, optimal target Thickness is $0.29{\mu}m$ and Largest energy of Light flux appears $4.59{\times}10^9$ x-ray flux.

• Progress in Medical Physics
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• v.17 no.4
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• pp.192-200
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• 2006

We evaluated the positional accuracy of the delivered beams to the target in a phantom by simulating the whole process of the radiation treatments Including CT scanning, planning and beam exposures with MLCs. For this purpose, a phantom was made to calibrate the alignment between the CT and the attached laser system. A new, convenient method was also devised to align the setup lasers in the treatment room. Film was used for the Identification of the delivered beam and analyzed with a homemade computer program. The positional differences between the target and the beam centers varied with the couch rotations. The accelerator we used showed a maximum discrepancy of 2.0 mm at the table angle of $295^{\circ}$. The same measurements based on the new isocenter from the Winston-Lutz test resulted in the maximum of 1.35 mm for all rotation angles. The evaluation of the differences between the target and the beam centers is useful for the treatment planning.

• Asian-Australasian Journal of Animal Sciences
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• v.25 no.6
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• pp.772-784
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• 2012

Marker-assisted gene pyramiding aims to produce individuals with superior economic traits according to the optimal breeding scheme which involves selecting a series of favorite target alleles after cross of base populations and pyramiding them into a single genotype. Inspired by the science of evolutionary computation, we used the metaphor of hill-climbing to model the dynamic behavior of gene pyramiding. In consideration of the traditional cross program of animals along with the features of animal segregating populations, four types of cross programs and two types of selection strategies for gene pyramiding are performed from a practical perspective. Two population cross for pyramiding two genes (denoted II), three population cascading cross for pyramiding three genes(denoted III), four population symmetry (denoted IIII-S) and cascading cross for pyramiding four genes (denoted IIII-C), and various schemes (denoted cross program-A-E) are designed for each cross program given different levels of initial favorite allele frequencies, base population sizes and trait heritabilities. The process of gene pyramiding breeding for various schemes are simulated and compared based on the population hamming distance, average superior genotype frequencies and average phenotypic values. By simulation, the results show that the larger base population size and the higher the initial favorite allele frequency the higher the efficiency of gene pyramiding. Parents cross order is shown to be the most important factor in a cascading cross, but has no significant influence on the symmetric cross. The results also show that genotypic selection strategy is superior to phenotypic selection in accelerating gene pyramiding. Moreover, the method and corresponding software was used to compare different cross schemes and selection strategies.

• The Journal of the Acoustical Society of Korea
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• v.22 no.6
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• pp.425-433
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• 2003

Acoustic Echo Canceller (AEC) is a signal processing system for removing unwanted echo signals in teleconference and hands-free communication. Least mean square (LMS) algorithm is one of the adaptive echo cancellation algorithms and it has been most attractive because of its simplicity and robustness. However, the convergence properties of the LMS algorithm degrade with highly correlated input signals such as speech. For this reason, transform-domain adaptive filtering algorithm was introduced to decorrelate the colored input samples by using the orthogonal transform matrix such as DCT, DFT and then LMS adaptive filtering process is applied. In this paper, we propose a MLT domain adaptive echo canceller base on the MLT (Modulated lapped Transform) orthogonal transform matrix. The proposed algorithm achieves high decorrelation efficiency and fast convergence speed via modulated lapped transform of size 2NXN instead of NXN unitary transform such as DCT, DFT, Hadamad and it is applied to the acoustical echo cancellation system. Form the computer simulation with both synthesis and real speech, the proposed MLT domain adaptive echo canceller shows approximately twice faster convergence speed and 20∼30 ㏈ ERLE improvements over the DCT frequency domain acoustic echo cancellation system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.