• Title/Summary/Keyword: power-efficient design

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Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

  • Kim, Yoon-Jin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.318-328
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    • 2011
  • Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

Power Estimation by Using Testability (테스트 용이도를 이용한 전력소모 예측)

  • Lee, Jae-Hun;Min, Hyeong-Bok
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.3
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    • pp.766-772
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    • 1999
  • With the increase of portable system and high-density IC, power consumption of VLSI circuits is very important factor in design process. Power estimation is required in order to estimate the power consumption. A simple and correct solution of power estimation is to use circuit simulation. But it is very time consuming and inefficient way. Probabilistic method has been proposed to overcome this problem. Transition density using probability was an efficient method to estimate power consumption using BDD and Boolean difference. But it is difficult to build the BDD and compute complex Boolean difference. In this paper, we proposed Propowest. Propowest is building a digraph of circuit, and easy and fast in computing transition density by using modified COP algorithm. Propowest provides an efficient way for power estimation.

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A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption

  • Lee, Hee-Sung;Kim, Eun-Tai
    • ETRI Journal
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    • v.30 no.6
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    • pp.799-806
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    • 2008
  • In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.

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Design of Power Factor Correction IC for 1.5kW System Power Module (1.5kW급 System Power Module용 Power Factor Correction IC 설계)

  • Kim, Hyoung-Woo;Seo, Kil-Soo;Kim, Ki-Hyun;Park, Hyun-Il;Kim, Nam-Kyun
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.499-500
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    • 2008
  • In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

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Design of an Efficient Power Manger through the cooperative Dynamic Power Management for Ad hoc Wireless Sensor Networks (Ad hoc 무선 센서네트워크에서의 효율 전력 매니지먼트에 관한 연구)

  • Jeon, Dong-Keun
    • The Journal of the Korea institute of electronic communication sciences
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    • v.6 no.6
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    • pp.809-814
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    • 2011
  • The major resource problem in sensor networks is energy efficiency. There are two major access methods to efficiently use energy. The first is to use dynamic power management (DPM). The second is to use energy efficient protocols. In DPM methods, the OS, the power manager, is responsible for managing the proper power state of CPU and each I/O with respect to the events, but the OS is not largely concerned about the internal operation of each network protocols. Also, energy efficient protocols are mainly focused on the power saving operation of the radio PHY. In addition, in wireless sensor network most of tasks are connected to communication. In such a situation, traditional power managers can waste unpredicted power. In this paper, we introduce an efficient power manger that can reduce a lot of unwanted power consumption through cooperative power management (CPM) in communication-related tasks between each units, such as radio, sensing unit, and CPU, for ad hoc wireless sensor nodes.

The trial installation test of PSS to Power Plant using Real Time Digital Simulator (RTDS를 이용한 PSS 현장 설치 모의 시험)

  • Hur, Jin;Kim, Dong-Joon;Moon, Young-Hwan;Shin, Jeong-Hoon;Kim, Tae-Kyun
    • Proceedings of the KIEE Conference
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    • 2002.07a
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    • pp.59-62
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    • 2002
  • Before a developed digital Power System Stabilizer(PSS) is installed to real power system, an efficient trial test for installing PSS is needed. In this paper, the performance of developed digital PSS for a single hydro-turbine generator and infinite bus system has been investigated using Real Time Digital Simulator(RTDS) in order to install PSS to real power system practically. The test system was composed of RTDS, three phase voltage/current amplifier and the PSS and the test scheme provided a very efficient way to verify the design and control performance of a PSS to be applied to real power system. The trial installation test through AVR 3% step test and three fault analysis may be guaranteed to install PSS to real power system.

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Development of a Hydraulic Power Package Enclosed with an Electric Motor (모터 일체형 유압 파워 패키지의 개발)

  • Park, Y.H.;Lee, C.D.;Lee, J.K.
    • Journal of Power System Engineering
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    • v.4 no.3
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    • pp.55-61
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    • 2000
  • In this study, a new design of an one-body type of an unbalanced-fixed- displacement type vane pump combined with an induction type electric motor was suggested. By the application of the new design scheme, it was possible to reduce the number of parts of the pump system and to cut down the volume of power package than that of already-used products. The case in this study enabled efficient heat transfer and electricity insulation of hydraulic fluid. Thus oil moves through the inside of the package for cooling and returns to the reservoir. Because of this design, it was difficult to measure the shaft-input torque. Therefore the package overall efficiency in the paper was evaluated with a ratio of hydraulic power and electric power.

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A new efficient algorithm for test pattern compression considering low power test in SoC (SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘)

  • 신용승;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.85-95
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    • 2004
  • As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

Effects of hospital environment using health belief model in environmental management on preventive behaviors through responsiveness and health value (환경경영에서 건강신념모델을 이용한 병원환경이 대응성과 건강가치성을 통해 예방행동에 미치는 영향)

  • Jang, Googhyun;Hwang, Changyu;Song, Youngwoo
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.12 no.3
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    • pp.231-257
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    • 2016
  • Several efforts to replace the use of existing fossil energy resources have already been made around the world. As a result, a new industry of renewable energy has been created, and efficient energy distribution and storage has been promoted intensively. Among the newly explored renewable energy sources, the most widely used one is solar energy generation, which has a high market potential. An energy storage system (ESS) is a system as required. In this paper, the design and implementation of an ESS for the efficient use of power in stand-alone street lights is presented. In current ESS applied to stand-alone street lights, either 12V~24V DC (from solar power) or 110V~220V AC (from commercial power) is used to recharge power in systems with lithium batteries. In this study, an ESS that can support both solar power and commercial power was designed and implemented; it can also perform emergency recharge of portable devices from solar powered street lights. This system can maximize the scalability of ESSes using lithium batteries with efficient energy conversion, with the advantage of being an eco-friendly technology. In a ripple effect, it can also be applied to smart grids, electric vehicles, and new, renewable storage markets where energy storage technology is required.

An Improved Task Scheduling Algorithm for Efficient Dynamic Power Management in Real-Time Systems (실시간 시스템에서 효율적인 동적 전력 관리를 위한 태스크 스케줄링 알고리듬에 관한 연구)

  • Lee Won-Gyu;Hwang Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4A
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    • pp.393-401
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    • 2006
  • Energy consumption is an important design parameter for battery-operated embedded systems. Dynamic power management is one of the most well-known low-power design techniques. This paper proposes an online realtime scheduling algorithm, which we call energy-aware realtime scheduling using slack stealing (EARSS). The proposed algorithm gives the highest priority to the task with the largest degree of device overlap when the slack time exists. Scheduling result enables an efficient power management by reducing the number of state transitions. Experimental results show that the proposed algorithm can save the energy by 23% on average compared to the DPM-enabled system scheduled by the EDF algorithm.