• ETRI Journal
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• v.33 no.5
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• pp.780-790
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• 2011

This paper presents an efficient differential power analysis (DPA) countermeasure for the $Eta_T$ pairing algorithm over GF($2^n$). The proposed algorithm is based on a random value addition (RVA) mechanism. An RVA-based DPA countermeasure for the $Eta_T$ pairing computation over GF($3^n$) was proposed in 2008. This paper examines the security of this RVA-based DPA countermeasure and defines the design principles for making the countermeasure more secure. Finally, the paper proposes an efficient RVA-based DPA countermeasure for the secure computation of the $Eta_T$ pairing over GF($2^n$). The proposed countermeasure not only overcomes the security flaws in the previous RVAbased method but also exhibits the enhanced performance. Actually, on the 8-bit ATmega128L and 16-bit MSP430 processors, the proposed method can achieve almost 39% and 43% of performance improvements, respectively, compared with the best-known countermeasure.

• Journal of Power Electronics
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• v.12 no.3
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• pp.439-447
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• 2012

In this paper, an input-series auxiliary power supply scheme is proposed, which is suitable for high input voltage and multiple-output applications. The power supply scheme is based on a two-transistor forward topology, all of the series modules have a common duty ratio, all the switches are turned on and off simultaneously, and the whole circuit has a single power transformer. It does not require an additional controller but still achieves efficient input voltage sharing (IVS) for each series module through its inherent transformer-integration strategy. The IVS process of this power supply scheme is analyzed in detail and the design considerations for the related parameters are given. Finally, a 100W multiple-output auxiliary power supply prototype is built, and the experimental results verify the feasibility of the proposed scheme and the validity of the theoretical analysis.

• IE interfaces
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• v.16 no.2
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• pp.240-247
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• 2003

Generally, the assembly system relied on conveyor lines is efficient for mass production. But it is not efficient when the product types are often varying and their lot sizes are small. Especially, it is much inefficient for the assembly lines for the electronic products whose types are varying very often. This paper suggests the design of U-shaped assembly lines to replace the existing conveyor systems. The assembly line for the mini-cassette production is dealt with as a case study. The proposed procedure was successfully applied for the design of U-shaped lines. The developed method resulted in the improvement of the productivity such as the decrease of the man power and the cycle time, and the increase of the line utility.

• Nuclear Engineering and Technology
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• v.56 no.9
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• pp.3644-3653
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• 2024

Enhancing the capabilities of unmanned space exploration, such as satellite monitoring and space science missions, requires efficient and reliable nuclear power systems. A viable solution is found in the 1-10 kWe power level of space nuclear reactor power systems, offering advantages such as a manageable research and development process, and relatively low investment requirements. This paper introduces a conceptual design for a 5 kWe space nuclear reactor power system, outlining its components and characteristics. The study includes a thorough analysis of potential challenges, encompassing heat pipe failure accidents, re-entry scenarios, and weight estimation considerations. The results demonstrate that the proposed space nuclear reactor power system effectively meets the safety requirements. The total mass of the power system is estimated at approximately 1.5 tons, with a specific mass of around 300 kg/kWe. This research contributes valuable insights for the design of space nuclear reactor power systems operating within a similar power range.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.11-19
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• 2012

In this paper, we propose a power-efficient scheduling scheme for lightly loaded multicore processors which contain more processing cores than running tasks. The proposed scheme activates a portion of available cores and inactivates the other unused cores in order to save power consumption. The tasks are assigned to the activated cores based on a heuristic mechanism for fast task assignment. Each activated core executes its assigned tasks with the optimal clock frequency which minimizes the power consumption of the tasks while meeting their deadlines. Evaluation shows that the proposed scheme saves up to 78% power consumption of the previous method which activates as many processing cores as possible for the execution of the given tasks.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.66-71
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• 2022

The insulator used for the transmission line is a device that is bonded with a cap, pin, ceramic, and cement to withstand insulation capacity and mechanical load. The insulator design can help to reduce the dispersion of the electric field; thus, the optimization of today's design, especially as demanded power grows, is critical. The designs of four manufacturers were used to perform a comparative analysis. Under dry circumstances of the new product, an electric field distribution study was done with no pollutants attached. Manufacturer D's design has the best voltage uniformity of 24.33% and the arc length of 500 mm or more. Manufacturer C's design has an equalizing voltage of more than 2% higher than that of other manufacturers. The importance of the design of the insulator and the number of connections according to the installation conditions is very efficient for transmission lines that will increase in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Proceedings of the KIEE Conference
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• 2009.04a
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• pp.186-188
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• 2009

In this thesis, output voltage, current and power of solar module were classified by irradiation and module temperature from data of overall operating characteristics collected for one year in order to manage efficient photovoltaic generation system and deliver maximum power. In addition, from these data, correlations between irradiation, module temperature of photovoltaic cell and amount of power given by photovoltaic cell was quantitatively examined to deduce optimization of the design and construction of photovoltaic generation system. The results of this thesis can be summarized as follows. As output power characteristics according to a temperature range of 10$\sim$50[], output power was increased with an increase in temperature. Since output power increases with temperature increase, the result corresponds well to the related equation on temperature and output power.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.58-58
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• 2002

Recently Many technologies of the P.L.N (Power Line Network) are introduced for an efficient communication. P.L.N transmits information using power line channel. A medical information transmission system is proposed in this paper for the effective transmission. The Power Line Networks have an advantage in low cost because it uses existent power line. It can be easily applied anywhere that a power line socket is available. But the power line channel is very noisy, because many electronic devices in generate electronic noise in modulated signals. This problem should be considered carefully in the design of medical information transmission system using P.L.N. The proposed system can be applied...I propose a telemedicine system using the power line network.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1678-1688
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• 2016

This paper presents a capacitive power transfer (CPT) system using a Class-E resonant inverter. A Class-E resonant inverter is chosen because of its ability to perform DC-to-AC inversion efficiently while significantly reducing switching losses. The proposed CPT system consists of an efficient Class-E resonant inverter and capacitive coupling formed by two flat rectangular transmitter and receiver plates. To understand CPT behavior, we study the effects of various coupling distances on output power performance. The proposed design is verified through lab experiments with a nominal operating frequency of 1 MHz and 0.25 mm coupling gap. An efficiency of 96.3% is achieved. A simple frequency tracking unit is also proposed to tune the operating frequency in response to changes in the coupling gap. With this resonant frequency tracking unit, the efficiency of the proposed CPT system can be maintained within 96.3%-91% for the coupling gap range of 0.25-2 mm.