• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.29-34
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• 2015

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1305-1308
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• 1987

This paper presents a design of an optimized implantable biotelemetry system and the fabrication of custom CMOS LSI for implementing this system. The internal circuits of this system are fabricated on a single silicon chip with a size of $4{\times}5mm^2$. This LSI is designed and fabricated not only to get as small size and low power dissipation as possible, but also to have multiple function. Its main functions are to select one of implanted sensors and to accomplish ON - OFF power switching of an implanted battery by receiving appropriate Command signals and control signals fran external circuits. The internal system which was assembled on a bread-board using fabricated LSI chip is confirmed to work as designed. The total power dissipation of this interal system was $10.12{\mu}W$.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.316-321
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• 2000

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.391-397
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• 2006

We present investigations of a hybrid type superconducting fault current limiter (SFCL), which consists of transformers and resistive superconducting elements. The secondary windings of the transformer were separated into several electrically isolated circuits and linked inductively with each other by mutual flux, each of which has a superconducting current limiting element of $YBa_2Cu_3O_7$ (YBCO) stripes as a current limiting element. Simple connection in series of the SFCL elements tends to produce ill-timed quenching because of power dissipation unbalance between SFCL elements. Both electrical isolation and mutual flux linkage of the elements provides a solution to power dissipation unbalance, inducing simultaneous quench and current redistribution of the YBCO films. This design enables to increase the voltage rating of SFCL with given YBCO stripes.

• 한국정보통신학회논문지
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• 제10권9호
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• pp.1633-1640
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• 2006

수용 가능한 수준의 성능을 동시에 전달하고 분배하는 동안의 소비 전력을 줄이는 문제는 고성능 시스템의 설계분야에서는 더욱 더 결정 적 인 관심사로 받아지고 있다. 본 논문에서는 전력분배의 문제를 클럭 신호 발생과 분배의 관점에서 제시하고자 한다. 우리는 클럭 신호의 전력 효율성과 다른 응용제품 이외에도 무선통신의 회로에서도 찾아 검증하였다.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2004년도 한국우주과학회보 제13권2호
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• pp.270-273
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• 2004

The initial thermal analysis needs to be fast and efficient to reduce the feedback time for the optimal electronic equipment designing. In this study, a thermal model is developed by using power consumption measurement values of each functional breadboard, that is, semi-empirical power dissipation method. In modeling heat dissipated EEE parts, power dissipation is imposed evenly on the EEE part footprint area which is projected to the printed circuit board, and is called surface heat model. The application of these methods is performed in the development of a command and telemetry unit (CTU) for a geostationary satellite. Finally, the thermal cycling test is performed to verify the applied thermal analysis methods.

• 전자공학회논문지B
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• 제31B권8호
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• pp.172-180
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• 1994

Implantable biotelemetry systems are indispensable tools not only in animal research but also in clinical medicine as such systems enable the acquisition of otherwise unavailable physiological data. We present the manufacture of CMOS IC and its system for implantable multichannel biotelemeter system. The internal circuits of this system are designed not only to achieve as multiple functions and low power dissipation as possible but also to enable continuous measurement of physiological data. Its main functions are to enable continuous measurement of physiological data and to accomplish on-off power swiching of an implantable battery by receiving appropriate commanc signals from an external circuit. The implantable circuits of this system are designed and fabricated on a single silicon chip using $1.5\mu$m n-well CMOS process technology. The total power dissipation of implantable circuits for a continuous operation was 6.7mW and for a stand-by operation was 15.2$\mu$ W. This system used together with approriate sensors is expected to contribute to clinical medicine telemetry system of measuring and wireless transmitting such significant physiological parameters as pressure pH and temperature.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.232-234
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• 1996

The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.