• Title/Summary/Keyword: power dissipation

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The Technical Trend of Heat Dissipation for High Power LED Flood Light (고출력 LED 투광등의 방열 기술 동향)

  • Kim, Ki-Yun;Ham, Kwang-Keun
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2009.05a
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    • pp.214-217
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    • 2009
  • 본 논문에서는 고출력 LED 투광등의 방열 기술 동향을 살펴본다. 이를 위해 LED 방열에 사용되는 대표적 기술로서 LED 패키지 방열 기술, 공랭식 방열 기술, 수냉식 방열 기술, 열전 소자 방열 기술에 대한 기술적 특징을 분석하고 각각의 국내외 관련 기술 개발 현황을 제시한다.

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A Snubber Design for Low Power Dissipation and Overvoltage Limitation in Three-Level GTO Inverters (3-레벨 GTO 인버터를 위한 새로운 스너버회로 설계)

  • Suh, Jae-Hyeong;Suh, Bum-Seok;Hyun, Dong-Seok
    • Proceedings of the KIEE Conference
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    • 1994.11a
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    • pp.153-155
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    • 1994
  • This paper presents a new low loss snubber including the overvoltage snubber for three-level GTO inverters. The proposed snubber can not only minimizes the snubber loss and the number of components but also improve blocking voltage balancing problem between the inner and the outer GTOs.

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An Analysis of Power Dissipation of Value Prediction in Superscalar Processors (슈퍼스칼라 프로세서에서의 값 예측의 전력 소모 측정 및 분석)

  • 이명근;이상정
    • Proceedings of the Korean Information Science Society Conference
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    • 2002.10c
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    • pp.688-690
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    • 2002
  • 고성능 슈퍼스칼라 프로세서에서는 명령어 수준 병렬성(Instruction Level Parallelism, ILP)의 장애인 명령어간의 종속 관계 중 데이터 종속관계를 극복하기 위해 값 예측기를 이용하여 모험적으로 명령어들을 실행한다. 값 예측 시에 필요한 테이블 참조와 값 예측 실패 시 실행되는 잘못된 명령어의 실행은 프로세서의 부가적인 전력 소모를 요구한다. 본 논문에서는 값 예측기와 Cai-Lim의 전력모델을 슈퍼스칼라 프로세서 사이클 수준 시뮬레이터인 SimpleScalar 3.0 툴셋에 삽입하여 전력 소모량을 측정하고 분석한다.

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Study of Thermal Ageing Behavior of the Accelerated Thermally Aged Chlorosulfonated Polyethylene for Thermosetting Analysis (열경화성 분석을 위한 가속열화 된 Chlorosulfonated Polyethylene의 경년특성 연구)

  • Shin, Yong-Deok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.5
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    • pp.800-805
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    • 2017
  • The accelerated thermal ageing of CSPE (chlorosulfonated polyethylene) was carried out for 16.82, 50.45, and 84.09 days at $110^{\circ}C$, equivalent to 20, 60, and 100 years of ageing at $50^{\circ}C$ in nuclear power plants, respectively. As the accelerated thermally aged years increase, the insulation resistance and resistivity of the CSPE decrease, and the capacitance, relative permittivity and dissipation factor of those increase at the measured frequency, respectively. As the accelerated thermally aged years and the measured frequency increase, the phase degree of response voltage vs excitation voltage of the CSPE increase but the phase degree of response current vs excitation voltage decrease, respectively. As the accelerated thermally aged years increase, the apparent density, glass transition temperature and the melting temperature of the CSPE increase but the percent elongation and % crystallinity decrease, respectively. The differential temperatures of those are $0.013-0.037^{\circ}C$ and, $0.034-0.061^{\circ}C$ after the AC and DC voltages are applied to CSPE-0y and CSPE-20y, respectively; the differential temperatures of those are $0.011-0.038^{\circ}C$ and $0.002-0.028^{\circ}C$ after the AC and DC voltages are applied to CSPE-60y and CSPE-100y, respectively. The variations in temperature for the AC voltage are higher than those for the DC voltage when an AC voltage is applied to CSPE. It is found that the dielectric loss owing to the dissipation factor($tan{\delta}$) is related to the electric dipole conduction current. It is ascertained that the ionic (electron or hole) leakage current is increased by the partial separation of the branch chain of CSPE polymer as a result of thermal stress due to accelerated thermal ageing.

Generic optimization, energy analysis, and seismic response study for MSCSS with rubber bearings

  • Fan, Buqiao;Zhang, Xun'an;Abdulhadi, Mustapha;Wang, Zhihao
    • Earthquakes and Structures
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    • v.19 no.5
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    • pp.347-359
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    • 2020
  • The Mega-Sub Controlled Structure System (MSCSS), an innovative vibration passive control system for building structures, is improved by adding lead rubber bearings (LRBs) on top of the substructure. For the new system, a genetic algorithm is used to optimize the dynamic parameters and distributions of dampers and LRBs. The program uses various seismic performance indicators as optimization objectives, and corresponding results are compared. It is found that the optimization procedure for maximizing the energy dissipation ratio yields the best solutions, and optimized models have consistent seismic performances under different earthquakes. Seismic performances of optimized MSCSS models with and without LRBs, as well as the traditional Mega-Sub Structure model, are evaluated and compared under El Centro wave, Taft wave and 20 other artificial waves. In both elastic and plastic analysis, the model with LRBs shows significantly smaller story drift and horizontal acceleration than those of the other two models, and fewer plastic hinges are developed during severe earthquakes. Energy analysis also shows that LRBs installed in proper locations increase the deformation and energy dissipation of dampers, thereby significantly reduce the kinetic, potential, and hysteretic energy in the structure. However, LRBs do not have to be mounted on all the additional columns. It is also demonstrated that LRBs at unfavorable locations can decrease the energy dissipation for dampers. After LRBs are installed, the optimal damping coefficient and the optimal damping exponent of dampers are reduced to produce the best damping effect.

Low-power FFT/IFFT Processor for Wireless LAN Modem (무선 랜 모뎀용 저전력 FFT/IFFT프로세서 설계)

  • Shin Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11A
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    • pp.1263-1270
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    • 2004
  • A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz@2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz@2.5-V.

Papers : A Study on Heat Mitigation for KOMPSAT - 2 High Heat Dissipation Electronic Boxes (논문 : 다목적 실용위성 2 호 고전력 소산 전장품의 열부하 완하에 관한 연구)

  • Park, Jin-Han;Jang, Yeong-Geun
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.30 no.3
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    • pp.77-86
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    • 2002
  • 위성은 일단 한 번 발사하고 나면 운용궤도상에서 수리 및 회수가 거의 불가능하기 때문에 위성에 들어가는 모든 개발 부품들은 완벽한 설계, 충분한 해석, 고 작업도의 제작, 그리고 다양한 시험이 반드시 수반되어야 한다. 위성시스템에서 전자 소자의 신뢰성에 영향을 주는 인자는 다양하다. 과도한 열은 전자소자의 실패를 유발해서 결과적으로는 전체 위성의 실패를 유도할 수 있다. 이 논문에서는 다목적 실용위성 2호의 고전력 소산 전장품의 열부하 완화를 위한 방안을 경우별로 연구 비교하였다. 고전력 소산 전장품의 열부하를 완화하기 위해서는 하우징 두께의 증가가 필요하며, 전력조절기의 다이오드나 트랜지스터처럼 전력소산이 큰 소자에 대해서는 장착위치를 변경하거나 장착 부분의 열전도율을 증가시키는 방법이 필요하다. 또한 전력조절기처럼 장착면이 좁은 경우에는 복사의 영향이 크며, 이러한 전장품의 열부하를 완화하기 위해서는 주위 벽면의 온도를 낮추거나 하우징 표면 방사율을 증가시키는 방법이 효과적임이 알 수 있다.

Chaos on the Rocking Vibration of Rigid Block Under Two Dimensional Sinusodial Excitation (In the Case of No Sliding Occurrence) (2차원 정현파 가진을 받는 강체블록의 록킹진동에 있어서의 카오스 (미끄럼이 없는 경우에 대하여))

  • 정만용;김정호;김지훈;양광영;양인영
    • Journal of the Korean Society of Safety
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    • v.14 no.2
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    • pp.42-51
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    • 1999
  • This research deals with the non-linearities associated with impact and sliding for the rocking behavior of rigid block subjected to two dimensional excitation of horizontal and vertical direction. The non-linearities examined of impact between block and base: The transition of two governing rocking equations, the abrupt reduction in kinetic energy associated with impact. In this study, the rocking vibration system of two types are considered for several friction condition. One is the undamped rocking vibration system, disregarding energy dissipation at impact and the other is the damped rocking system, including energy dissipation at impact. The response analysis by non-dimensional rocking equation is carried out for the change of excitation amplitude. The chaos responses were discovered in the wide response region, particularly, in the case of high vertical excitation and their chaos characteristics are examined by Poincare map, power spectra and Lyapunov Exponent. The complex behavior of chaos response, in the phase space, were illustrated by Poincare map. Therefore, Poincare map will be a significant material in order to understand chaos of rocking system.

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A study on the design of the boosted voltage cenerator for low power DRAM (저전력 DRAM 구현을 위한 boosted voltage generator에 관한 연구)

  • 이승훈;주종두;진상언;신홍재;곽계달
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.530-533
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    • 1998
  • In this paper, a new scheme of a boosted voltage generator (BVG) is designed for low powr DRAM's. The designed BVG can supply stable $V_{pp}$ using a new circuit operting method. This method controls charge pumping capability by switching the supply voltage and ring oscillator frequency of driving circuit, so the BVG can save area and reduce the powr dissipation during $V_{pp}$ maintaining period. The charge pumping circuit of the BVG suffers no $V_{T}$ loss and is to be applicable to low-voltage DRAM's. $V_{pp}$ level detecting circuit can detect constant value of $V_{pp}$ against temperature variation. The level of $V_{pp}$ varies -0.55%~0.098% during its maintaining period. Charge pumping circuit can make $V_{pp}$ level up to 2.95V with $V_{cc}$ =1.5V. The degecting level of $V_{pp}$ level detecting circuit changes -0.34% ~ 0.01% as temperature varies from -20 to 80.deg. C. The powr dissipation during V.$_{pp}$ maintaining period is 4.1mW.W.1mW.

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Thermal Management on 3D Stacked IC (3차원 적층 반도체에서의 열관리)

  • Kim, Sungdong
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.5-9
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    • 2015
  • Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.