• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.21-24
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• 2002

This paper presents a fully integrated, wide tuning range differential CMOS voltage-controlled oscillator, tuned by pMOS-varactors. VCO utilizing a novel tuning scheme is reported. Both coarse digital tuning and fine analog tuning are achieved using pMOS-varactors. The VCO were implemented in a 0.18-fm standard CMOS process. The VCO tuned from 1.8㎓ to 2.55㎓ through 2-bit digital and analog input. At 1.8V power supply voltage and a total power dissipation of 8mW, the VCO features a phase noise of -126㏈c/㎐ at 3㎒ frequency offset.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.77-81
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• 2002

This paper demonstrates a CMOS downconversion mixer for 2.4GHz ISM band applications. The mixer, implemented in a 0.18um CMOS process, is based on the CMOS Gilbert Cell mixer, With a 2.5GHz local oscillator and a 2.45GHz RF input, the measurement results exhibit power conversion gam of -6dB, IIP3 of -6dBm, input $P_{-1dB}$ of -15 dBm, and power dissipation in mixer core of 2.7 mW with 0㏈m LO power and 1.8V supply voltage.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.276-279
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• 2015

This paper presents two 3-stage D-band stacked amplifiers developed in a $0.13-{\mu}m$ SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.418-422
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• 2011

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2089-2092
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• 1999

Partial discharge(PD) tests were performed both when the pumped storage generator(rated 13.8kV and 220MVA) was on-line and off-line. This generator has been equipped with 12 bus coupler sensors in directional mode. PD tests were conducted using partial discharge analyzer(PDA), partial discharge meter(PDM) and digital partial discharge detector. PDA showed that the patterns of the normalized quantity number(NQN) and the partial discharge magnitude are in accord with on-line and off-line. The insulation condition was estimated by diagnostic tests(off-line) such as PD magnitude and dissipation factor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Transactions of The Korea Fluid Power Systems Society
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• v.6 no.4
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• pp.24-32
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• 2009

For a design of on/off solenoid actuator for valve actuating, designer must have the experimental knowledge as well as general electromagnetic formulas to design object. It is possible for theoretical knowledge to do the out-line design, but it is impossible to optimal design without experimental knowledge which only can be achieved through many repeated experiments. In addition, in present on/off type solenoid actuator field, the smaller, lightening, lower consumption power, high response time are effected as the most important design factor. So, experimental knowledge is more needed for optimal design of solenoid actuator. In this study, we derived the governing equations for optimal design of on/off solenoid actuator for valve actuating and developed a design program composed electromagnetic theories and experimental parameter values for inexperienced designers. And we proved the propriety of this program by experiments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.279-280
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• 2008

Accelerated aging tests were conducted under laboratory conditions on two generator stator bars. Electrical stress is applied in No. 1 model stator bar. Electrical and thermal stresses are applied in No. 2 model stator bar. As aging times increased from 0 to 4780h, diagnostic tests were performed on No. 1 and No. 2 model stator bars. Diagnostic tests included AC current, dissipation factor(tan$\delta$) and partial discharge magnitude. The ${\Delta}tan{\delta}$ and $\Deta$I of No. 1 and No. 2 model stator bars increased with increased in aging time.