• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1399-1402
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• 2003

Paul Hocker has developed new attacks based on the electric consumption of cryptographic device such as smartcard that performs cryptographic computation. Among those attacks, the Differential Power Analysis(DPA) is one of the most impressive and most difficult to avoid. By analysing the power dissipation of encryption in a device, the secret information inside can be deduced. This paper presents that Advanced Encryption Standard(AES) is highly vulnerable to DPA and readily leaks away all secret keys through the experimental results for DPA. After all, it is required an implementation of the AES algorithm that is not vulnerable to DPA. We also propose countermeasures that employ asynchronous circuit.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.45-48
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• 2003

Recently the PDP is the most remarkable media for a next generation display device. In this paper, we proposed the PDP dedicated DC-DC converter using a new soft switching method because the PDP has a lot of power dissipation so we need to develope. The proposed converter using one transformer has soft switching and a advantage to lower voltage stress in switch and also is predicted to have high power efficiency. we proposed the principles and theory using the zero voltage switching and verified the validity through a simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.351-354
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• 2011

This paper was carried about thermal analysis for high efficiency point contact solar cell. Therefore, we carried about 2-D device and process simulator according to design and process parameters. As a result of simulations, power transfer efficiency have decreased more increasing temperature. Especially, power transfer efficiency of room temperature have been showed 25%. The other hand, power transfer efficiency of 350 K kalvin temperature have been showed 20%. Therefore, we will considered design with thermal dissipation of device.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.9
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• pp.1312-1316
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• 2014

The color and the installation position of the LED lamp for night voyage of the ship are changed by the purpose of it. The power dissipation occurs because a navigation light is on and off or continuously on. In addition, in case that the light is produced by operating generator in the ship, it's very inefficient except that it's on a voyage. Therefore in this dissertation, we construct auxiliary power system for the LED lamp of the ship, producing and developing a module, a panel, and a charging system using Dye-sensitize Solar Cell.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.369-373
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• 2004

Recently the PDP is the most remarkable media for a next generation display device. In this paper, we proposed the PDP dedicated DC-DC converter using quasi-resonant method because the PDP has a lot of power dissipation so we need to develope. The proposed converter using one transformer has soft switching and a advantage to lower voltage stress in switch and also is predicted to have high power efficiency. we proposed the principles and theory using the zero voltage switching and verified the validity through a experiment.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.5-10
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• 2002

We have analized the inverse class-F and class-F amplifiers using their waveforms. From the analytic equations derived from the analysis, we have calculated tole efficiencies, output powers, DC power dissipations, and optimum fundamental load impedances of the inverse class-F and class-F amplifiers. We also have compared them for various operation conditions, which include the same peak current, saute DC power dissipation, same fundamental RF output power, and same fundamental load impedance with different Ron(on-resistance). These analyses have clearly shown the performance limitations, advantages, and guide to the optimized design of the inverse class-F amplifiers.

• Journal of Power Electronics
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• v.13 no.5
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• pp.779-786
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• 2013

A highly efficient sustaining driver is proposed for plasma display panels (PDPs). When the PDP is charged and discharged, the proposed sustaining driver employs an address voltage source used in an addressing period. A voltage source is used for fully charging the panel to the sustaining voltage, and an initial inductor current helps the panel discharge to 0 V. The resonance between the panel and an inductor is made by shifting the voltage and current bias level when charging and discharging the panel. As a result, the proposed circuit can reduce power consumption, switching loss, heat dissipation, and production cost. Experimental results of a 42-inch PDP are provided to verify the operation and features of the proposed circuit.

• Proceedings of the KIEE Conference
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• 2003.07e
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• pp.52-54
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• 2003

By having the proposed circuit using a smaller one with a small reactor, the output voltage is boosted-up and improves the input of the current waveform. Therefore, we are able to follow the harmonics guidelines Greater power and efficiency is obtained from the proposed circuit. This also reduces some switching loss and holds the over-shooting by using the inverter of eliminated dead-time HPWM which is a non-linear impedance of the circuit to make up the diodes, the capacitance, and the reactor. We compared the conventional PWM inverter and proposed HPWM inverter.