• 제목/요약/키워드: post metallization annealing

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Forming Gas Post Metallization Annealing of Recessed AlGaN/GaN-on-Si MOSHFET

  • Lee, Jung-Yeon;Park, Bong-Ryeol;Lee, Jae-Gil;Lim, Jongtae;Cha, Ho-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권1호
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    • pp.16-21
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    • 2015
  • In this study, the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET were investigated. The device employed an ICPCVD $SiO_2$ film as a gate oxide layer on which a Ni/Au gate was evaporated. The PMA process was carried out at $350^{\circ}C$ in forming gas ambient. It was found that the device instability was improved with significant reduction in interface trap density by forming gas PMA.

PECVD SiON 절연막을 이용한 4H-SiC MOS 소자 특성 연구 (Study on Characteristics of 4H-SiC MOS Device with PECVD SiON Insulator)

  • 김현섭;이재길;임종태;차호영
    • 전기전자학회논문지
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    • 제22권3호
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    • pp.706-711
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    • 2018
  • 본 논문에서는 플라즈마 화학기상증착 (plasma enhanced chemical vapor deposition, PECVD) 방식을 이용한 산질화규소(Silicon oxynitride, SiON) 절연체를 이용하여 4H-SiC metal-oxide-semiconductor (MOS) 소자를 제작하고 특성 분석을 수행하였다. 제작된 소자는 금속 증착 후 열처리 과정 (post metallization annealing, PMA)을 통하여 트랩 밀도가 크게 감소하는 것을 확인하였으며, 특히 $500^{\circ}C$의 forming gas 분위기에서 열처리 된 소자의 경우 매우 뛰어난 MOS 특성을 나타내었다. 본 연구를 통하여 4H-SiC MOS 구조를 위한 대체 게이트 절연체로써 PECVD SiON의 활용 가능성을 확인 할 수 있었다.

화학적기상증착법에 의한 구리박막의 전기전도도 개선에 관한 연구 (A Study on the Enhancement of Electrical Conductivity of Copper Thin Films Prepared by CVD Technology)

  • 조남인;김용석;김창교
    • 한국전기전자재료학회논문지
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    • 제13권6호
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    • pp.459-466
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    • 2000
  • For the applications in the ultra-large-scale-integration (ULSI) metallization processing copper thin films have been prepared by metal organic chemical vapor deposition (MOCVD) technology on TiN/Si substrates. The films have been deposited with varying the experimental conditions of substrate temperatures and copper source vapor pressures. The films were then annealed in a vacuum condition after the deposition and the annealing effect to the electrical conductivity of the films was measured. The grain size and the crystallinity of the films were observed to be increased by the post annealing and the electrical conductivity was also increased. The best electrical property of the copper film was obtained by in-situ annealing treatment at above 40$0^{\circ}C$ for the sample prepared at 18$0^{\circ}C$ of the substrate temperature.

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SOI 기판에서 Silicide의 후속 공정 열처리 영향에 대한 연구 (Study of Post-silicidation Annealing Effect on SOI Substrate)

  • 이원재;오순영;김용진;장잉잉;종준;이세광;정순연;김영철;왕진석;이희덕
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.3-4
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    • 2006
  • In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

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$Ta/TaN_x$ Metal Gate Electrodes for Advanced CMOS Devices

  • Lee, S. J.;D. L. Kwong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권3호
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    • pp.180-184
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    • 2002
  • In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

다결정 CdTe박막의 저저항 접축을 위한 배선금속 및 열처리방법의 효과에 관한 연구 (Effects of lead metal and annealing methods on low resistance contact formation of polycrystalline CdTe thin film)

  • 김현수;이주훈;염근영
    • E2M - 전기 전자와 첨단 소재
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    • 제8권5호
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    • pp.619-625
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    • 1995
  • Polycrystalline CdTe thin film has been studied for photovoltaic application due to the 1.45 eV band gap energy ideal for solar energy conversion and high absorption coefficient. The formation of low resistance contact to p-CdTe is difficult because of large work function(>5.5eV). Common methods for ohmic contact to p-CdTe are to form a p+ region under the contact by in-diffusion of contact material to reduce the barrier height and modify a p-CdTe surface layer using chemical treatment. In this study, the surface chemical treatment of p CdTe was carried out by H$\_$3/PO$\_$4/+HNO$\_$3/ or K$\_$2/Cr$\_$2/O$\_$7/+H$\_$2/SO$\_$4/ solution to provide a Te-rich surface. And various thin film contact materials such as Cu, Au, and Cu/Au were deposited by E-beam evaporation to form ohmic contact to p-CdTe. After the metallization, post annealing was performed by oven heat treatment at 150.deg. C or by RTA(Rapid Thermal Annealing) at 250-350.deg. C. Surface chemical treatments of p-CdTe thin film improved metal/p-CdTe interface properties and post heat treatment resulted in low contact resistivity to p-CdTe.Of the various contact metal, Cu/Au and Cu show low contact resistance after oven and RTA post-heat treatments, respectively.

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MOS 소자의 대체 게이트 산화막으로써 $HfO_{2}/HfSi_{x}O_{y}$ 의 구조 및 전기적 특성 분석 (Structural and electrical characterizations of $HfO_{2}/HfSi_{x}O_{y}$ as alternative gate dielectrics in MOS devices)

  • 강혁수;노용한
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.45-49
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    • 2001
  • We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

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MOS 소자를 위한 $HfO_3$게이트 절연체와 $WSi_2$게이트의 집적화 연구 (Investigation of $WSi_2$ Gate for the Integration With $HfO_3$gate oxide for MOS Devices)

  • 노관종;양성우;강혁수;노용한
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.832-835
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    • 2001
  • We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

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Process Temperature Dependence of Al2O3 Film Deposited by Thermal ALD as a Passivation Layer for c-Si Solar Cells

  • Oh, Sung-Kwen;Shin, Hong-Sik;Jeong, Kwang-Seok;Li, Meng;Lee, Horyeong;Han, Kyumin;Lee, Yongwoo;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권6호
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    • pp.581-588
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    • 2013
  • This paper presents a study of the process temperature dependence of $Al_2O_3$ film grown by thermal atomic layer deposition (ALD) as a passivation layer in the crystalline Si (c-Si) solar cells. The deposition rate of $Al_2O_3$ film maintained almost the same until $250^{\circ}C$, but decreased from $300^{\circ}C$. $Al_2O_3$ film deposited at $250^{\circ}C$ was found to have the highest negative fixed oxide charge density ($Q_f$) due to its O-rich condition and low hydroxyl group (-OH) density. After post-metallization annealing (PMA), $Al_2O_3$ film deposited at $250^{\circ}C$ had the lowest slow and fast interface trap density. Actually, $Al_2O_3$ film deposited at $250^{\circ}C$ showed the best passivation effects, that is, the highest excess carrier lifetime (${\tau}_{PCD}$) and lowest surface recombination velocity ($S_{eff}$) than other conditions. Therefore, $Al_2O_3$ film deposited at $250^{\circ}C$ exhibited excellent chemical and field-effect passivation properties for p-type c-Si solar cells.

질산산화법을 이용한 SiO2/Si 구조의 계면결함 제거 (Removal of Interface State Density of SiO2/Si Structure by Nitric Acid Oxidation Method)

  • 최재영;김도연;김우병
    • 한국재료학회지
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    • 제28권2호
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    • pp.118-123
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    • 2018
  • 5 nm-thick $SiO_2$ layers formed by plasma-enhanced chemical vapor deposition (PECVD) are densified to improve the electrical and interface properties by using nitric acid oxidation of Si (NAOS) method at a low temperature of $121^{\circ}C$. The physical and electrical properties are clearly investigated according to NAOS times and post-metallization annealing (PMA) at $250^{\circ}C$ for 10 min in 5 vol% hydrogen atmosphere. The leakage current density is significantly decreased about three orders of magnitude from $3.110{\times}10^{-5}A/cm^2$ after NAOS 5 hours with PMA treatment, although the $SiO_2$ layers are not changed. These dramatically decreases of leakage current density are resulted from improvement of the interface properties. Concentration of suboxide species ($Si^{1+}$, $Si^{2+}$ and $Si^{3+}$) in $SiO_x$ transition layers as well as the interface state density ($D_{it}$) in $SiO_2/Si$ interface region are critically decreased about 1/3 and one order of magnitude, respectively. The decrease in leakage current density is attributed to improvement of interface properties though chemical method of NAOS with PMA treatment which can perform the oxidation and remove the OH species and dangling bond.