• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.209.2-209.2
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• 2013

We proposed and fabricated zinc oxide thin-film transistors (TFTs) employing 4-mercaptophenol (4MP) doped ZnO by atomic layer deposition (ALD) that results in highly stable and high performance. The 4MP concentration in ZnO films were varied from 1.7% to 5.6% by controlling Zn:4MP pulses. The n-type carrier concentrations in ZnO thin films were controlled from $1.017{\times}10^{20}/cm^3$ to $2.903{\times}10^{17}/cm^3$ with appropriate amount of 4MP doping. The 4.8% 4MP doped ZnO TFT revealed good device mobility performance of 8.4 $cm^2/Vs$ and the on/off current ratio of 106. Such 4MP doped ZnO TFTs exhibited relatively good stability (${\Delta}V_{th}$: 2.4 V) under positive bias-temperature stress while the TFTs with only ZnO showed a 4.3 ${\Delta}V_{th}$ shift, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.682-687
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• 2014

We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage ($V_{th}$) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the $V_{th}$ and the on-current were decreased. The on-current reduction was caused by the positive shift of the $V_{th}$ and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.354-355
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• 2013

최근 디스플레이 분야에서 amorphous InGaZnO (a-IGZO) thin film transistors (TFTs)는 a-Si:H에 비해 비정질 상태에서도 비교적 높은 이동도를 가지고 다결정 Si 반도체에 비해 저온공정이 가능하고 대면적화가 용이한 장점 때문에 주목받고 있다. 또한 넓은 밴드갭을 가지기 때문에 가시광선 영역에서 투명하여 투명소자에도 응용이 가능하다. 본 연구에서는 RF magnetron sputtering법을 이용하여 RF power의 변화에 따라 IGZO 박막의 positive bias stress (PBS)에 대한 안정성을 조사하였다. 소결된 타겟으로는 In:Ga:ZnO를 각각 2:2:1 mol%의 조성비로 소결하여 이용하였고, 공정 조건은 초기 압력 Torr, 증착 압력 Torr, Ar：O2=18：12 sccm로 고정하였다. 공정 변수로는 130 W, 150 W, 170 W, 200 W로 변화를 주어 실험을 진행하였다. PBS 측정은 gate bias를 10 V로 고정하여 stress 시간을 각각 0, 30, 100, 300, 1,000, 3,000, 7,000초를 적용하였다. 측정 결과 RF power가 증가할수록 문턱전압의 변화량이 증가하는 것을 보였다. 130 W의 경우 4.47 V의 변화량을 보였지만 200 W의 경우는 10.01 V로 증가되어 나타났다. 따라서 RF power을 낮추어 만들어진 소자의 경우 RF power를 높여 만들어진 소자에 비해 PBS에 대한 안정성이 더 높은 결과를 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.33-39
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• 2015

In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.15 no.1
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• pp.95-112
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• 2020

This paper is to investigate how cognitive bias of college students and entrepreneurs relates to perceived risks and entrepreneurial opportunities that represent uncertainty, and how various cognitive bias and entrepreneurial efficacy In the same way. The purpose of this study is to find improvement points of entrepreneurship education for college students and to suggest problems and improvement possibilities in the decision making process of current entrepreneurs. This empirical study is a necessary to improve the decision-making of individuals who want to start a business at the time when various attempts are made to activate the start-up business and increase the sustainability of the existing SME management. And understanding of the difference in opportunity evaluation, and suggests that it is necessary to provide good opportunities together with the upbringing of entrepreneurs. In order to achieve the purpose of the study, questionnaires were conducted for college students and entrepreneurs. A total of 363 questionnaire data were obtained and demonstrated through structural equation modeling. This study confirms that there is some relationship between perceived risk and cognitive bias. Overconfidence and control illusions among cognitive bias have a significant relationship between perceived risk and wealth. Especially, it is confirmed that control illusion of college students has a significant relationship with perceived risk. Second, cognitive bias demonstrated some significant relationship with opportunity evaluation. Although we did not find evidence that excess self-confidence is related to opportunity evaluation, we have verified that control illusions and current status bias are related to opportunity evaluation. Control illusions were significant in both college students and entrepreneurs. Third, perceived risk has a negative relationship with opportunity evaluation. All students, regardless of whether they are college students or entrepreneurs, judge opportunities positively if they perceive low risk. Fourth, it can be seen from the college students 'group that entrepreneurial efficacy has a moderating effect between perceived risk and opportunity evaluation, but no significant results were found in the entrepreneurs' group. Fifth, the college students and entrepreneurs have different cognitive bias, and they have proved that there is a different relationship between entrepreneurial opportunity evaluation and perceived risk. On the whole, there are various cognitive biases that are caused by time pressure or stress on college students and entrepreneurs who have to make judgments in uncertain opportunities, and in this respect, they can improve their judgment in the future. At the same time, university students can have a positive view of new opportunities based on high entrepreneurial efficacy, but if they fully understand the intrinsic risks of entrepreneurship through entrepreneurial education and fully understand the cognitive bias present in direct entrepreneurial experience, You will get a better opportunity assessment. This study has limitations in that it is based on the fact that university students and entrepreneurs are integrated, and that the survey respondents are selected by the limited random sampling method. It is necessary to conduct more systematic research based on more faithful data in the absence of the accumulation of entrepreneurial research data. Second, the translation tools used in the previous studies were translated and the meaning of the measurement tools might not be conveyed due to language differences. Therefore, it is necessary to construct a more precise scale for the accuracy of the study. Finally, complementary research should be done to identify what competitive opportunities are and what opportunities are appropriate for entrepreneurs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.267.1-267.1
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• 2016

본 연구에서는 nematic 액정의 종류 중 하나인 5CB (4-Cyano-4'-pentylbiphenyl) 물질을 박막 트랜지스터 (TFT)의 passivation 층으로 사용했을 때 그 전기적 특성향상을 확인하였다. RF-magnetron sputtering법으로 증착된 비정질 InGaZnO 박막을 활성층으로 사용한 TFT를 제작하여 그 활성층 위에 drop형식으로 passivation 하였다. 그 결과, drain current (I_DS)가 약 10배 정도 증가하고, linear region(V_D=0.5V)에서 mobility와 subthreshold slope(SS)이 각각 6.7에서 12.2, 0.3에서 0.2로 향상되는 것이 보였다. 이것은 gate bias가 인가되었을 때 freedericksz 전이를 통한 액정의 배향과 이때 형성된 dipole 형성에 의한 것으로 보이며, 이러한 LC의 배향은 편광현미경을 통하여 표면과 수직으로 배향한다는 사실을 확인 할 수 있었고 이 LC-passivation된 a-IGZO TFT의 전기적 특성의 향상에 대한 mechanism을 제시하였다. 그리고 배향한 LC가 가지는 dipole에 의해 bias stress 상황에서 독특한 electron trapping과 recovery의 증폭효과가 나타났다. V_G=+20V의 positive gate bias stress를 1000s동안 가했을 때, passivation되지 않은 a-IGZO TFT의 경우 +4V의 threshold voltage shift(${\Delta}V$_TH)가 발생되었고, 바로 -20V의 negative gate bias를 30s간 가해주었을 때 -2.5V의 ${\Delta}V$_TH가 발생하였다. 반면 LC-passivation된 a-IGZO TFT의 경우 각각 +5V와 -4V의 ${\Delta}V$_TH로 더 큰 변화를 가져왔다. 이러한 LC에 의한 electron trapping/recovery 증폭효과에 대한 model을 제시하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.265.2-265.2
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• 2016

Oxide thin film transistors (TFTs) have attracted considerable interest for gate diver and pixel switching devices of the active matrix (AM) liquid crystal display (LCD) and organic light emitting diode (OLED) display because of their high field effect mobility, transparency in visible light region, and low temperature processing below $300^{\circ}C$. Recently, oxide TFTs with polycrystalline In-Ga-O(IGO) channel layer reported by Ebata. et. al. showed a amazing field effect mobility of $39.1cm^2/Vs$. The reason having high field effect mobility of IGO TFTs is because $In_2O_3$ has a bixbyite structure in which linear chains of edge sharing InO6 octahedral are isotropic. In this work, we investigated the characteristics and the effects of oxygen partial pressure significantly changed the IGO thin-films and IGO TFTs transfer characteristics. IGO thin-film were fabricated by rf-magnetron sputtering with different oxygen partial pressure ($O_2/(Ar+O_2)$, $Po_2$)ratios. IGO thin film Varies depending on the oxygen partial pressure of 0.1%, 1%, 3%, 5%, 10% have been some significant changes in the electrical characteristics. Also the IGO TFTs VTH value conspicuously shifted in the positive direction, from -8 to 11V as the $Po_2$ increased from 1% to 10%. At $Po_2$ was 5%, IGO TFTs showed a high drain current on/off ratio of ${\sim}10^8$, a field-effect mobility of $84cm^2/Vs$, a threshold voltage of 1.5V, and a subthreshold slpe(SS) of 0.2V/decade from log(IDS) vs VGS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.458-462
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• 2011

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.