• 한국전기전자재료학회논문지
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• 제19권6호
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• pp.507-511
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• 2006

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

• 한국재료학회지
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• 제5권2호
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• pp.203-207
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• 1995

Polysilicon this film transistors (poly-Si TFTs) with different channel dimensions were fabricated on low-temperature crystalized amorphous silicon films and on as-deposited polysilicon films. The electrical characteristics of these TFTs were characterized and compared. The performance of the TFTs fabricated on the solid-phase crystalized amophous silicon films ws showon to be superior to that of the TFTs fabricated on the as-deposited polysilicon films. It was found that the performance of poly-Si TFTs depends strongly on the material characteristics of the polysilicon films used as the active layers, but only weakly on the channel dimensions.

• 전자공학회논문지A
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• 제32A권5호
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.

• Journal of Information Display
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• 제6권1호
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.293-293
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• 2005

The differences between floating and grounded body effects in polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated by making a body contact. The floating body effects such as kink effect, subthreshold slope change, and body current characteristics are explained and modeled by impact ionization, which causes source body turn on, and activates the parasitic bipolar junction transistors (BJTs). These effects become crucial for channel lengths of 4㎛ or shorter. Our data show that making a body contact reduces kink effects significantly and identifies impact ionization mechanism in polysilicon TFTs.

• 한국정밀공학회지
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• 제21권7호
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• pp.171-178
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• 2004

Techniques and procedures are presented for measuring mechanical properties on thin-film Polysilicon. Narrow platinum lines are deposited 250 ${\mu}{\textrm}{m}$ apart on tensile specimens that are 3.5 ${\mu}{\textrm}{m}$ thick and 600 ${\mu}{\textrm}{m}$ wide. Load is applied by a piezo-actuator and by hanging weights. Strain is measured by an ISDC at temperatures up to 500 $^{\circ}C$. Measurements of the elastic modulus with jig modifications, loading speed and temperature change are presented first. And then, the preliminary data for the coefficient of thermal expansion and creep behavior are presented as a reference.

• 한국전기전자재료학회논문지
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• 제11권7호
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• pp.522-526
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• 1998

We have fabricated a LDD structured polysilicon thin film transistor with low leakge current and the optimized LDD length has been obtained. The device performance is improved is improved by hydrogen passivation process. The on.off current ratio of poly0Si TFT s with $0.5{\mu}m$ and $1.0{\mu}m$ LDD length is much higher than that of conventional structured device due to the decrease of leakege current. The optimized LDD length may be $0.5{\mu}$ from the experimental data such as on/off current ratio, threshold voltage and hydrogenation effect.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1075-1078
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• 2007

Negative Bias Temperature Instability (NBTI) in Eximer Laser Annealing (ELA) based Low Temperature polysilicon (LTPS) Thin-Film Transistors (TFT) was investigated. Even though NBTI is generally appeared in devices with thin gate oxide, the TFT with gate oxide thickness of 120 nm, relatively thick, also showed NBTI effect and dynamic NBTI effect is dependent on operational frequency.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
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• pp.127-127
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• 2002