• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• ETRI Journal
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• v.7 no.4
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• pp.11-14
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• 1985

A polysilicon self-aligned bipolar n-p-n transistor structure is described, which can be used in high speed and high packing density LSI circuits The emitter of this transistor is separated less than $0.4\mum$ with base contact by polysilicon self-align technology. Through all the process, the active region of this device is not damaged. therefore a high performance device is obtained. Using the transistor with $3.0\mum$ design rules, a CML ring oscillator has per-gate minimum propagation delay time of 400 ps at 2.7 mW power consumption condition.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.786-793
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• 1987

This paper describes the design and fabrication of the polysilicon selfaligned bipolar transistor with 1.6\ulcorner epitaxy and SWAMI isolation technologies. This transistor has two levels of polysilicon. Also emitter and adjacent edge of polysilicon base contact of this PSA device are defined by the same mask, and emitter feature size is 2x4 \ulcorner. DC characteristic of the fabricated transistor was evaluated and analyzed for the SPICE input parameters. The minimum propagation delay time per gate of 330 ps at 1mW was obtained with 41 stage CML ring oscillator.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.7
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

• Journal of Information Display
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• v.6 no.1
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.