• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.309-314
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• 1999

The magnetized helical resonator plasma etcher has been built. Electron density and temperature were measured as functions of rf source power, axial magnetic field, and pressure. The results show electron density increases as the magnetic field increases and reached $2\times1012cm^{-3}$,/TEX>. The oxide etch rate and selectivity to polysilicon were investigated as the above mentioned conditions and self-bias voltage. We can obtain the much improved oxide etch selectivity to polysilicon (60 : 1) by applying the external axial weak magnetic field in magnetized helical resonator plasma etcher.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1990.10a
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• pp.55-59
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10$\mu\textrm{m}$) were fabricated using RTP(Rapid Thermal Processor) and hydrogen passivation. The N+ Source, drain and gate were annealed and recrystallized using RTP at temperature of 1000$^{\circ}C$-1100$^{\circ}C$. But the active areas were now specially crystallized before growing the gate oxide. Without the hydrogen passivation, excellent transistor characteristics (ON/OFF=5${\times}$10$\^$6/, s=85mv/dec, I$\_$L/=51pA/$\mu\textrm{m}$) were obtained for 1.5$\mu\textrm{m}$ MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.795-800
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• 1986

High value sheet resistance (Rs, 350\ulcorner/ -80K\ulcorner/) born implanted polysilicon resistors were fabricated under process conditions compatible with bipolar integrated circuits fabrications. This paper includes studies of sensitivity of Rs to doping concentration, the effect of thermal annealing temperature on Rs, temperature coefficient of resistance (TCR), the effect of polysilicon thickness on Rs and the Rs variation within a run and between runs.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.7-12
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• 1995

• Korean Journal of Materials Research
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• v.3 no.6
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• pp.638-644
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• 1993

The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.

• Journal of the Korean Recycled Construction Resources Institute
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• v.2 no.2
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• pp.166-171
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• 2014

This experimental study considers manufacturing method of the non-portland cement matrix for the light-weight building materials using blast furnace slag, paper ash, fly ash and polysilicon sludge the industrial by-product. For the experiment, we used paper ash by means of the foaming agent and alkali activator to make non-portland cement light-weight matrix. Various specimens were prepared with different types and addition ratios of the alkali activator. Then, the properties of these specimens were investigated by compressive strength test, bulk specific gravity. As a results, it was judged that experiment results of non-portland cement matrix with specific waste resources and alkali activators were useful as basic data for mixtures design and evaluation properties of lightweight non-portland cement building material.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Current Photovoltaic Research
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• v.12 no.2
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• pp.31-36
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• 2024

Passivating contacts are a promising technology for achieving high efficiency Si solar cells by reducing direct metal/Si contact. Among them, a polysilicon (poly-Si) based passivating contact solar cells achieve high passivation quality through a tunnel oxide (SiO_x) and poly-Si. In poly-Si/SiO_x based solar cells, the passivation quality depends on the amount of dopant in-diffused into the bulk-Si. Therefore, our study fabricated cells by inserting silicon oxide (SiO₂) as a doping barrier before doping and analyzed the barrier effect of SiO₂. In the experiments, p⁺ poly-Si was formed using spin on dopant (SOD) method, and samples ware fabricated by controlling formation conditions such as existence of doping barrier and poly-Si thickness. Completed samples were measured using quasi steady state photoconductance (QSSPC). Based on these results, it was confirmed that possibility of achieving high V_oc by inserting a doping barrier even with thin poly-Si. In conclusion, an improvement in implied V_oc of up to approximately 20 mV was achieved compared to results with thicker poly-Si results.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.150-150
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• 2009

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1991-1993
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• 1996

This paper describes a standardized micromachinung project (SMP) performed at Seoul National University (SNU). The SNU SMP uses a 3-mask, 2-polysilicon surface micromaching process. The entire process is performed at SNU Inter-University Semiconductor Research Institute(ISRC). In this first SNU SMP attemp, 16 $1cm^2$ cells containing different designs were fabricated.