• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1772-1775
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• 2000

We have fabricated poly-Si TFTs by two-step crystallizaton. Poly-Si films have been prepared by furnace annealing(FA) and rapid thermal annealing(RTA) followed by subsequent the post-annealing, excimer laser annealing. The measured crystallinity of RTA and FA annealed poly-Si film is 77% and 68.5%, respectively. For two-step annealed poly-Si film, the crystallinity has been drastically to 87.7% and 86.3%. The RMS surface roughness from AFM results have been improved from 56.3${\AA}$ to 33.5${\AA}$ after post annealing. The measured transfer characteristics of the two-step annealed poly-Si TFTs have been improved significantly for the both FA-ELA and RTA-ELA. Leakage currents of two-step annealed poly-Si TFTs are lower than that of the devices by FA and RTA. From these results, we can describe the fact that the intra-grain defects has been cured drastically by the post-annealing.

• 전자공학회논문지D
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• 제35D권12호
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• pp.68-74
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• 1998

본 논문에서는 electron cyclotron resonance (ECR) N₂O-플라즈마 산화막을 게이트 산화막으로 사용한 다결정 실리콘 박막 트랜지스터 (TFT)의 성능과 단채널 특성에 대하여 연구하였다. ECR NE₂O-플라즈마 게이트 산화막을 사용한 소자는 열산화막을 이용한 경우에 비해 우수한 성능과 억제된 단채널 효과를 나타낸다. 얇은 ECR N2O-플라즈마 산화막을 사용하여 n채널 TFT의 경우 3 ㎛, p채널 TFT의 경우 1㎛ 게이트 길이까지 문턱 전압 감소가 없는 소자를 얻었다. 이러한 특성 향상은 부드러운 계면, passivation 효과, 그리고 계면과 박막 내부에 존재하는 강한 Si ≡ N 결합 등에 기인한다.

• 한국재료학회지
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• 제6권6호
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• pp.589-604
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• 1996

화학증착기에 의한 실리콘막의 증착에서 증착기의 기초 진공도는 잔류가스로부터 실리콘 막내로 유입되는 oxygen, carbon과 같은 분순물의 양을 결정하며, 따라서 증착 거동 및 막의 결정성에 영향을 줄 수 있는 공정 변수이다. 본 연구에서는 고진공 화학증착기를 이용하여 기초 진공도는 비정질 실리콘의 증착과 결정화에 미치는 영향을 조사하였다. 높은 기초 진공도는 비정질/결정질 천이 증착온도의 감소를 가져왔다. 또한 비정질 실리콘막의 결정화 속도 및 박막 결정성을 향상시키는 것으로 조사되었다. 이와 같은 기초 진공도의 영향은 증착시 잔류가스에 함유되는 O, C과 같은 불순물의 영향으로 설명될 수 있었다. 기초 진공도에 따른 실리콘 막의 결정성 향상은 다결정 실리콘 박막 트렌지스터의 구동 특성을 향상시키는 것으로 조사되었다. 기초 진공도가 10-3Torr에서 10-5Torr 로 증가함에 따라 전자 이동도는 17$\textrm{cm}^2$/V.s에서 25$\textrm{cm}^2$/V.s로 증가하였으며 누설전류는 감소하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1289-1291
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• 1993

The hydrogenation effects on characteristics of polycrystalline silicon thin film transistors(poly-Si TFT's) of which the channel length varies from $2.5{\mu}m\;to\;20{\mu}m$ and poly-Si layer thickness is 50, 100, and 150 nm was investigated. After 1 hr hydrogenation annealing by PECVD, the threshold voltage shift decreased dependent on the channel length, but channel width may not alter the threshold voltage shift. In addition to channel length, the active poly-Si layer thickness may be an important parameter on hydrogenation effects, while gate poly-Si thickness may do not influence on the characteristics of TFT's. Considering our experimental results, we propose that channel length and active poly-Si layer thickness may be a key parameters of hydrogenation of poly-Si TFT's.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.471-474
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• 2000

A flat type microgas sensor was fabricated on the p-type silicon wafer with low stress S $i_3$ $N_4$, whose thickness is 2${\mu}{\textrm}{m}$ using MEMS technology and its characteristics were investigated. W $O_3$thin film as a sensing material for detection of N $O_2$gas was deposited using a tungsten target by sputtering method, followed by thermal oxidation at several temperatures (40$0^{\circ}C$~$600^{\circ}C$) for one hour. N $O_2$gas sensitivities were investigated for the W $O_3$thin films with different annealing temperatures. The highest sensitivity when operating at 20$0^{\circ}C$ was obtained for the samples annealed at $600^{\circ}C$. As the results of XRD analysis, the annealed samples had polycrystalline phase mixed with triclinic and orthorhombic structures. The sample exhibit higher sensitivity when the system has less triclinic structure. The sensitivities, $R_{gas}$ $R_{air}$ operating at 20$0^{\circ}C$ to 5 ppm N $O_2$of the sample annealed at $600^{\circ}C$ were approximately 90. 90.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.28-29
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• 2006

When photovoltaic module is used for a long time, its performance decreases due to several reasons. In this paper, we focus on the possibilities mainly contributing to the degraded efficiency of the polycrystalline silicon photovoltaic modules. The analysis is based on the modules that have been used for 15 years. These are two main reasons that cause the efficiency degradation, the corrosion and thermal decomposition. The former phenomenon of electrode is mainly due to the moisture from damaged back sheet in some module. However the other reason of the degraded efficiency comes from the thermal decomposition, which can not be observed from the outside but only by experiment. In this study, the comparison between the efficiency of normal modules and degradation modules is presented. Module having degraded cell was seen to cause increase of series resistance by about 80%, in comparison to normal samples efficiency which reduce by about 20%. This study shows that the effects of series resistances on module performance are critical. These effects must be understood and taken into consideration when analyzing performance degradation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.143.2-143.2
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• 2013

Nanomechanical and electrical properties of vanadium dioxide (VO2) thin films across thermal-driven phase transition are investigated with ultra-high vacuum atomic force microscopy. VO2 thin films have been deposited on the n-type heavily doped silicon wafer by pulsed laser deposition. X-ray diffraction reveals that it is textured polycrystalline with preferential orientation of (100) and (120) planes in monoclinic phase. As the temperature increases, the friction decreased at the temperature below the transition temperature, and then the friction increased as increasing temperature above the transition temperature. We attribute this observation to the combined effect of the thermal lubricity and electronic contribution in friction. Furthermore, the dependence of nanoscale conductance on the local pressure was indicated at the various temperatures, and the result was discussed in the view of pressure-induced metal-insulator transition.

• 대한금속재료학회지
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• 제48권7호
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• pp.660-666
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• 2010

30 nm thick Ni layers were deposited on a glass substrate by e-beam evaporation. Subsequently, 30 nm or 60 nm ${\alpha}-Si:H$ layers were grown at low temperatures ($<220^{\circ}C$) on the 30 nm Ni/Glass substrate by catalytic CVD (chemical vapor deposition). The sheet resistance, phase, microstructure, depth profile and surface roughness of the $\alpha-Si:H$ layers were examined using a four-point probe, HRXRD (high resolution Xray diffraction), Raman Spectroscopy, FE-SEM (field emission-scanning electron microscopy), TEM (transmission electron microscope) and AES depth profiler. The Ni layers reacted with Si to form NiSi layers with a low sheet resistance of $10{\Omega}/{\Box}$. The crystallinty of the $\alpha-Si:H$ layers on NiSi was up to 60% according to Raman spectroscopy. These results show that both nano-scale NiSi layers and crystalline Si layers can be formed simultaneously on a Ni deposited glass substrate using the proposed low temperature catalytic CVD process.

• 대한건축학회논문집:구조계
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• 제35권8호
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• pp.177-184
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• 2019

Recently, electric power usages and peak loads from buildings are increasing due to higher outdoor air temperatures and/or abnormal climate during the summer period. As one of the eco-friendly measures, a renewable energy system has been received much attention. Particularly, interest on a photovoltaic (PV) system using solar energy has been rapidly increasing in a building sector due to its broad applicability. In using the PV system, one of important factors is the PV efficiency. The normal PV efficiency is determined based on the STC(Standard Test Condition) and the NOCT(Nominal Operating Cell Temperature) performance test. However, the actual PV efficiency is affected by the temperature change at the module surface. Especially, higher module temperatures generally reduce the PV efficiency, and it leads to less power generation from the PV system. Therefore, the analysis of the relation between the module temperature and PV efficiency is required to evaluate the PV performance during the summer period. This study investigates existing algorithms for calculating module surface temperatures and analyzes resultant errors with the algorithms by comparing the measured module temperatures.