• 한국세라믹학회지
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• 제40권3호
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• pp.317-321
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• 2003

The grain-boundary microcracking materials in the system A1$_2$Ti $O_{5}$ -ZrTi $O_4$(ZAT) is influenced by the thermal expansion anisotropy. The range of ZAT compositions investigated had showed very low thermal expansions of 0.3~1.3$\times$10$^{-6}$K compared to 8.29$\times$10$^{-6}$K of pure ZrTi $O_4$and 0.68$\times$10$^{-6}$K of polycrystalline A1$_2$Ti $O_{5}$ , respectively, compared with the theoretical thermal expansion coefficient for a single crystal of A1$_2$Ti $O_{5}$ , 9.70$\times$10$^{-6}$K. The low thermal expansion and microcraking temperature are apparently due to a combination of thermal contraction and expansion caused by the large thermal expansion anisotropy of the crystal axes of the A1$_2$Ti $O_{5}$ phase.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권6호
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• 한국표면공학회지
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• 제36권1호
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• pp.14-21
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• 2003

Thin films of ZrO$_2$ and TiO$_2$ were deposited on Si(100) substrates using RF magnetron sputtering technique. To study an influence of the sputtering parameters, systematic experiments were carried out in this work. XRD data show that the $ZrO_2$ films were mainly grown in the [111] orientation at the annealing temperature between 800 and $1000^{\circ}C$ while the crystal growth direction was changed to be [012] at above $1000^{\circ}C$. FT-IR spectra show that the oxygen stretching peaks become strong due to $SiO_2$ layer formation between film layers and silicon surface after annealing, and proved that a diffusion caused by either oxygen atoms of $ZrO_2$ layers or air into the interface during annealing. Different crystal growth directions were observed with the various deposition parameters such as annealing temperature, RF power magnitude, and added $O_2$ amounts. The growth rate of $TiO_2$ thin films was increased with RF power magnitude up to 150 watt, and was then decreased due to a sputtering effect. The maximum growth rate observed at 150 watt was 1500 nm/hr. Highly oriented, crack-free, stoichiometric polycrystalline $TiO_2$<110> thin film with Rutile phase was obtained after annealing at $1000^{\circ}C$ for 1 hour.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2011년도 춘계학술대회 및 Fine pattern PCB 표면 처리 기술 워크샵
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• pp.142-142
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• 2011

Epitaxial $CuCrO_2$ thin films have been grown on single crystal substrate of c-plane $Al_2O_3$, $SrTiO_3$, YSZ and Quarts by laser ablation of a $CuCrO_2$ target using 266nm radiation from a Nd:YAG laser. X-ray measurements indicate that the $CuCrO_2$ grows epitaxially on all substrate, with its orientation dependent on the kinds of substrates. Most of the layer were polycrystalline with (001), (015) and random as the dominant surface orientation on c-plane YSZ, $SrTiO_3$ and quarts substrate, respectively. (001) orientated $CuCrO_2$ grows on C-plane $Al_2O_3$ and YSZ substrate, (015) orientated $CuCrO_2$ films are found on c-plane $SrTiO_3$ substrate and random orientated $CuCrO_2$ films grows on quarts substrate. These data are compared with the in-plane orientation and the mismatch of the $CuCrO_2$ and each substrate lattices in an attempt to relate the preferred orientation to the plane of the sapphire on which it is grown. Further characterization show that the grain size of the films increases for a substrate temperature increase, whereas the electrical properties of $CuCrO_2$ thin films depend upon their crystalline orientation.

• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• 한국전기전자재료학회논문지
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• 제21권9호
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• pp.795-800
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• 2008

A sublimation method using the SiC seed crystal and SiC powder as the source material is commonly adopted to grow SiC bulk single crystal. However, it has proved to be difficult to achieve the high quality crystal and the process reliability because SiC single crystal should be grown at very high temperature in closed system. The present research was focused to improve SiC crystal quality grown by PVT method through using the new inner guide tube. The new inner guide tube was designed to prevent the enlargement of polycrystalline region into single crystalline region and to enlarge the diameter of SiC single crystal. The 6H-SiC crystals were grown by conventional PVT process. The seed adhered on seed holder and the high purity SiC source materials are placed on opposite side in sealed graphite crucible surrounded by graphite insulation. The SiC bulk growth was conducted around 2300 $^{\circ}C$ of growth temperature and 50 mbar in an argon atmosphere of growth pressure. The axial thermal gradient across the SiC crystal during the growth was estimated in the range of 15${\sim}$20 $^{\circ}C$/cm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1263-1264
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• 2007

자계 유도 고상결정화(FESPC)를 이용하여 제작한 다결정실리콘(poly-Si) 박막 트랜지스터(TFT)는 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)보다 뛰어난 전기적 특성과 우수한 안정성을 지닌다. $V_{DS}$ = -0.1 V에서 채널 폭과 길이가 각각 $5\;{\mu}m$, $7\;{\mu}m$인 P형 TFT의 이동도(${\mu}$)와 문턱 전압($V_{TH}$)은 각각 $31.98\;cm^2$/Vs, -6.14 V 이다. FESPC TFT는 일반 poly-Si TFT에 비해 채널 내 결정 경계 숫자가 많아서 상대적으로 열악한 특성을 가진다. 채널 길이 $5\;{\mu}m$인 TFT의 $V_{TH}$는 채널 길이 $18\;{\mu}m$ 소자의 $V_{TH}$보다 1.36V 작지만, 일반적으로 큰 값이다. 이 현상은 채널에 다수의 결정 경계가 존재하고, 수평 전계가 크기 때문이다. 수평 전계가 증가하면, 결정 경계의 전위 장벽 높이가 감소하게 되는데, 이는 DIGBL 효과이다. ${\mu}$의 증가에 따라서, 드레인 전류가 증가하고 $V_{TH}$은 감소한다. 활성화 에너지($E_a$)는 드레인 전압과 결정 경계의 수에 따라 변하는데, 드레인 전압이 크거나 결정 경계의 수가 감소하면 $E_a$는 감소한다. $E_a$가 감소하면 $V_{TH}$가 감소한다. 유리기판 위의 FESPC를 이용한 P형 poly-Si TFT의 $V_{TH}$는 채널의 길이와 $V_{DS}$에 영향을 받는다. 증가한 수평 전계가 결정 경계에서 에너지 장벽을 낮추는 효과를 일으키기 때문이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.282-283
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• 2005

Ion beam assisted deposition(IBAD) technique was used to produce biaxially textured polycrystalline MgO thin films for high critical current YBCO coated conductor. Hastelloy tapes were continuous electropolished with very smooth surface for IBAD-MgO deposition, RMS roughness of Hastelloy tape values below 2 nm and local slope of less than $1^{\circ}$. After the polishing of the tape an amorphous $Y_2O_3$ and $Al_2O_3$ are deposited Biaxially textured MgO was deposited on amorphous layer bye-beam evaporation with a simultaneous bombardment of high energy ions. We had developed the RHEED to measure in-situ biaxial texture of film surface as thin as tens angstrom. And also ex-situ characterization of buffer layers was studied using XRD and SEM. The full-width at half maximum(FWHM) out of plane texture of IBAD-MgO template is $4^{\circ}$.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• 한국전기전자재료학회논문지
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• 제27권12호
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• pp.815-819
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• 2014

Aluminum nitride (AlN) thin film and TiN film as a buffer layer were deposited on INCONEL 600 substrate by reactive RF magnetron sputtering at room temperature(R.T.) under 25~75% $N_2/Ar$ atmosphere. The as-deposited AlN films at 25~50% $N_2/Ar$ showed a polycrystalline phase of hexagonal AlN, and an amorphous phase. The peak of AlN (002) plane, which was determinant on a performance of piezoelectric transducer, became strong with increasing the $N_2/Ar$ ratio. Any change in the preferential orientation of the as-deposited AlN films was not observed within our $N_2$ concentration range. The piezoelectric sensing properties of AlN module were performed using pressure-voltage measurement system. The output signal voltage of AlN module showed a linear behavior between 20~80 mV in 1~10 MPa range, and the pressure-sensing sensitivity was calculated as 3.6 mV/MPa.