• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.91-92
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• 2007

이 논문에서는 다양한 채널길이에 따른 n-채널 다결정 실리콘 TFT의 특징을 보고한다. Excimer laser annealing (ELA)를 이용한 다결정 실리콘은 디스플레이의 재료로써 줄은 특성을 갖는다. 유리기판 위에 buffered oxide 층을 올리고 ELA 처리를 하여 다결정 실리콘을 제작 하였다. 그 위에 $SiO_2$, $SiN_x$를 증착시켜 n-채널 다결정 실리콘 TFT를 만들었다. 다양한 채널의 길이에 따른 n-채널 TFT의 문턱전압 ($V_{TH}$), ON/OFF 전류비($I_{ON}/I_{OFF}$), 포화 전륙(IDSAT)를 조사하였다. 그 결과 채널의 길이가 짧은 소자에서 더 줄은 TFT의 특징이 나타난다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.69-74
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• 2004

System-on-glass technology made with low temperature poly-Si TFT has been rapidly advancing in recent years. We have developed a low-power, narrow edged frame, 1.9inch system-on-glass LCD which fully integrates a 16-bit RGB interface driver and all power circuits required for driving the LCD. In this paper, the latest poly-Si TFT circuit technologies used in the newly developed LCD are discussed. The development trends are also reviewed.

• Journal of Information Display
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• 제2권2호
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• pp.22-26
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• 2001

This paper presents the idea of staggered voting for the efficient TMR implementation of shift register chains for improving the yield of Poly-Si TFT-LCD driving circuits. The paper discusses the characteristic features of staggered voting and performs a quantitative evaluation of its effectiveness. Staggered voting allows us to improve the reliability of a single-voter TMR chain significantly when the probability of a voter failure is not negligible.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.933-936
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• 2000

N-channel poly-Si TFT, processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5um and 3um poly-Si TFT’s are 3.3V, 37V respectively. With the threshold voltage shift, the degradation of transconductance and subthreshold swing is also observed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.116-116
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• 2011

오늘날 표시장치는 경량, 고밀도, 고해상도 대면적화의 요구에 의해 TFT-LCD의 발전이 이루어졌다. TFT에는 반도체 재료로서, Poly-Si을 사용하는 Poly-Si TFT와 a-Si:H를 이용하는 a-Si;H TFT가 있는데 a-Si는 $350^{\circ}C$ 이하의 저온으로 제작이 가능하여 많이 사용되고 있다. 이러한 방향에 맞추어 bottom gate 구조의 a-Si TFT 실험을 진행하였다. P-type silicon substrate ($0.01{\sim}0.02{\Omega}-cm$)에 gate insulator 층인 SiNx (SiH4 : NH3 = 6:60)를 200nm 증착하였다. 그리고 그 위에 active layer 층인 a-Si (SiH4 : H2 : He =2.6 : 10 : 100)을 다른 RF power를 적용하여 100 nm 증착하였다. 그 위에 Source와 Drain 층은 Al 120 nm를 evaporator로 증착하였다. active layer, gate insulator 층은 ICP-CVD 장비를 이용하여 증착하였으며, 공정온도는 $300^{\circ}C$ 로 고정하였다. active layer층 증착시 RF power는 100W, 300W, 500W, 600W로 가변하였고, width/length는 100 um/8um로 고정하였다. 증착한 a-Si layer층을 Raman spectroscope, SEM 측정 하였으며, TFT 제작 후, VG-ID, VD-ID 측정을 통해 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio를 비교해 보았다.

• 전자공학회논문지A
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• 제32A권2호
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• pp.324-331
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• 1995

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.

• 전자공학회논문지D
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• 제35D권5호
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• pp.48-53
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• 1998

Poly-Si TFT's could be fabricated on glass substrates by metal induced lateral crystallization (MILC) method at 450.deg. C. Channel area of the poly-Si TFT's was laterally crystallized from source and drain areas, where a thn nickel film was deposited. Dopants activation for the formation of source and drain region could be achieved by thermal annealing at 450.deg. C after the ion mass doping of phosphorus. The field effect mobility of thus formed N-channel poly-Si TFT's was 76cm$^{2}$/Vs, and the on/off current ratio was higher than 7E6.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.61-67
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• 2006

본 논문에서는 Poly-Si의 불규칙한 Grain boundary 분포로 인해 발생하는 문턱전압의 변화에 대해서도 일정한 전류를 흘려줄 수 있는 전류원을 제안하였다. 기존의 문턱전압 보상 전류원에 비해 넓은 입력전압 범위에서도 포화영역의 특성이 매우 향상되었으며 문턱전압의 변화에 따른 전류의 오차를 감소시킬 수 있었다. 마지막으로 HSPICE 시뮬레이션 과정을 통해 Poly-Si TFT의 특성곡선과 제안된 전류원의 특성곡선을 비교하였으며 각각의 입력전압에 대한 문턱전압의 변화에 따른 출력전류의 상대오차를 측정하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.