• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1836-1838
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• 1999

다결정 실리콘 박막 트랜지스터(TFT)의 누설전류를 줄이기 위하여 채널의 중간에 선택적으로 도핑된 영역을 가진 새로운 다결정 실리콘 TFT를 제안한다. 제안된 TFT에서는 채널의 일부가 선택적으로 도핑되어 채널 전체에 걸리는 전기장이 재분배된다. 제안된 n-채널 TFT는 $V_{GS}$<0, $V_{DS}$>0인 조건에서, 대부분의 전기장이 드레인 접합에 형성되는 공핍영역과, 도핑된 영역 중 소오스 쪽과 도핑되지 않은 채널 사이에 형성되는 공핍영역에 각각 나뉘어 걸린다. 기존의 다결정 실리콘 TFT와 비교할 때 드레인 접합에서 걸리는 전기장은 1/2로 감소하였고, 이에 따라 드레인 접합에서 생성되는 전자-홀 쌍도 현저히 감소하였다. 더구나 제안된 TFT의 온-전류는 기존의 TFT와 비교했을 때 거의 같거나 약간 감소하였으며 이에 따른 온/오프 전류비가 현저히 향상되었음을 실험을 통해 확인할 수 있었다.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1011-1014
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• 2004

In this paper, we present a new DC-DC converter for gate driver circuit in low temperature poly-Si TFT technology. It is composed of a newly developed charge pump circuit and a regulator circuit. When the input voltage is 5V, the efficiency of a positive charge pump used in the DC-DC converter and that of a negative charge pump is 69.0% and 57.1%, respectively. The output voltage of DC-DC converter varies 200mV when the target voltages of DC-DC converter are 9V, -6V and the threshold voltage of TFTs varies ${\pm}$ 0.5V.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.783-786
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• 2004

We have developed a 470 x 235ppi poly-Si TFT LCD with a novel pixel arrangement, called HDDP (Horizontally Double-Density Pixels), for high-resolution 2D and 3D autostereoscopic display. 3D image quality is especially high in a lenticular-lens-equipped 3D mode because both horizontal resolution and vertical resolution are high, and because these resolutions are equal. 3D and 2D images can be displayed simultaneously in the same picture. In addition, 3D images can be displayed anywhere and 2D characters can be made to appear at different depths with perfect legibility. No switching of 2D/3D modes is necessary, and the design's thin and uncomplicated structure makes it especially suitable for mobile terminals.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1301-1304
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• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.399-402
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.7
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• pp.522-526
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• 1998

We have fabricated a LDD structured polysilicon thin film transistor with low leakge current and the optimized LDD length has been obtained. The device performance is improved is improved by hydrogen passivation process. The on.off current ratio of poly0Si TFT s with $0.5{\mu}m$ and $1.0{\mu}m$ LDD length is much higher than that of conventional structured device due to the decrease of leakege current. The optimized LDD length may be $0.5{\mu}$ from the experimental data such as on/off current ratio, threshold voltage and hydrogenation effect.

• Journal of Information Display
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• v.7 no.3
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• pp.9-12
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.75-80
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• 2004

By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.