• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.261-264
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• 1999

This paper presents a circuit-level method to deal with transistor nonuniformity In this method, which is called transistor slicing, a transistor is implemented as a parallel connection of multiple smaller transistors. The paper analyzes the method and demonstrates that transistor slicing can effectively reduce the nonuniformity in TFT mobility and threshold voltage. The method is particularly useful in Implementing analog functions using poly-silicon TFTs which show a significant level of nonuniformity.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.44 no.5
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• pp.21-31
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• 2012

In this study, we modified the surface of ground calcium carbonate (GCC) with polyelectrolytes with different molecular weight using Layer-by-Layer (LbL) multilayering technique and investigated its effect on the paper properties. Polydiallydimethylammonium chloride (poly-DADMAC) and poly sodium 4-styrene sulfonate (PSS) which have different molecular weights were used for LbL multilayering. Zeta potential and particle size of the LbL modified GCC were measured. After preparation of handsheets, their structural and mechanical properties were evaluated. The zeta potential and average particle size of the modified GCC were affected by the molecular weight of anionic polyelectrolyte (PSS). The zeta potential was higher and the particle size was smaller when GCC was treated by PSS with high molecular weight compared to the case with low molecular weight of PSS. The tensile and internal bond strength of the handsheets was increased with an increase in the number of layers on GCC particles, but the molecular weight of polyelectrolyte did not significantly affect the paper strength.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.553-556
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• 1999

This paper presents a proper condition to achieve above 19 % conversion efficiency using PC1D simulator. Cast poly-Si wafers with resistivity of 1 $\Omega$-cm and thickness of 250 ${\mu}{\textrm}{m}$ were used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 ${\mu}{\textrm}{m}$, front surface recombination velocity 100 cnt/s, sheet resistivity of emitter layer 100 $\Omega$/$\square$, BSF thickness 5 ${\mu}{\textrm}{m}$, doping concentration 5$\times$10$^{19}$ cm$^3$ . Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %. Further details of simulation parameters and their effects to cell characteristics are discussed in this paper.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Polymer(Korea)
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• v.39 no.3
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• pp.461-467
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• 2015

This paper reports the combined effects of the triblock copolymer surfactant poly(ethylene glycol)-poly(propylene glycol)-poly(ethylene glycol) (PEG-PPG-PEG) and imidazole on the opto-electrical and mechanical properties of poly(3,4-ethylenedioxythiophene) (PEDOT)-based thin films prepared via vapor phase polymerization (VPP) using ferric p-toluenesulfonate as a catalyst. Various PEDOT-based thin films were synthesized using PEG-PPG-PEG and imidazole alone and in combination to compare and correlate their effects on film properties. The improved conductivity of the PEDOT films was higher than $1300S{\cdot}cm^{-1}$ when the surfactant and imidazole were used together. The PEG-PPG-PEG chain length was also varied to identify the best conditions for the VPP-based preparation of PEDOT thin films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.25-35
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• 2001

In order to analyze the electrical characteristics of complicated thin film transistor-liquid crystal display (TFT-LCD) array circuits, it is indispensible to use simulation programs such as PSPICE and AIM-SPICE. In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT for SPICE simulations. This method was applied to two different types of poly-Si TFTs, fabricated by excimer laser annealing and silicide mediated crystallization methods, and yielded good fitting results to experimental data. Among the SPICE simulators, PSPICE has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT device model to the PSPICE simulator, and analyzed easily the electrical characteristics of pixels considering the line RC delay. The results of this work would contribute to efficient simulations of poly-Si TFT-LCD arrays.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• Journal of Sensor Science and Technology
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• v.26 no.6
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• pp.438-444
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• 2017

In this paper, we focus on optimization of the in-situ phosphorous (P) doping of low-pressure chemical vapor deposited (LPCVD) poly Si resistors for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $600^{\circ}C$. The deposited poly Si films were annealed by rapid thermal anneal (RTA) process at the temperature range from 900 to $1000^{\circ}C$ for 90s in nitrogen ambient to relieve intrinsic stress and decrease the TCR in the poly Si layer and get the Ohmic contact. After the RTA process, a roughness of the thin film was slightly changed but the grain size and crystallinity of the thin film with the increase in anneal temperature. The film annealed at $1,000^{\circ}C$ showed the behavior of Schottky contact and had dislocations in the films. Ohmic contact and TCR of $334.4{\pm}8.2$ (ppm/K) within 4 inch wafer were obtained in the measuring temperature range of 25 to $600^{\circ}C$ for the optimized 200 nm thick-poly Si film with width/length of $20{\mu}m/1,800{\mu}m$. This shows the potential of in-situ P doped LPCVD poly Si as a resistor for pressure sensor in harsh environment applications.

• Applied Chemistry for Engineering
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• v.24 no.1
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• pp.93-98
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• 2013

In this paper, four conducting polymers (poly[(N-butyl-phenothiazine)-sulfide] (PBPS), poly[(N-hexyl-phenothiazine)-sulfide] (PHPS), poly[(N-decyl-phenothiazine)-sulfide] (PDPS), and poly[(N-(2-ethylhexyl)-phenothiazine)-sulfide] (PEHPS)) were synthesized with a high temperature and high pressure reaction. The structures of synthesized polymers were confirmed by $^1H-NMR$ and characterized by UV-Vis, cyclic voltammetry, and GPC. From the UV-Vis absorption spectra, the ${\lambda}_{max}$ values of PBPS, PHPS, PDPS, and PEHPS were 338, 341, 340, and 334 nm, respectively and their optical band gaps were 3.11, 3.13, 3.16, and 3.05 eV, respectively. To evaluate the feasible applicability as a photovoltaic cell, the devices composed of for example, ITO/PEDOT : PSS/polymer (PBPS, PDPS) : $PC_{71}BM$ (1 : 3, w/w)/$BaF_2$/Ba/Al were fabricated using the blends of the PBPS and PDPS as a donor, and $PC_{71}BM$ as an acceptor. Then, the power conversion efficiencies (PCE) of devices were estimated as 0.076% of PBPS and 0.136% of PDPS by solar simulator.

• Journal of Sensor Science and Technology
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• v.16 no.6
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• pp.457-461
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• 2007

This paper describes the characteristics of poly (polycrystalline) 3C-SiC grown on $SiO_{2}$ and AlN substrates, respectively. The crystallinity and the bonding structure of poly 3C-SiC grown on each substrate were investigated according to various growth temperatures. The crystalline quality of poly 3C-SiC was improved from resulting in decrease of FWHM (full width half maximum) of XRD and FT-IR by increasing the growth temperature. The minimum growth temperature of poly 3C-SiC was $1100^{\circ}C$. The surface chemical composition and the electron mobility of poly 3C-SiC grown on each substrate were investigated by XPS and Hall Effect, respectively. The chemical compositions of surface of poly 3C-SiC films grown on $SiO_{2}$ and AlN were not different. However, their electron mobilities were $7.65{\;}cm^{2}/V.s$ and $14.8{\;}cm^{2}/V.s$, respectively. Therefore, since the electron mobility of poly 3C-SiC films grown on AlN buffer layer was two times higher than that of 3C-SiC/$SiO_{2}$, a AlN film is a suitable material, as buffer layer, for the growth of poly 3C-SiC thin films with excellent properties for M/NEMS applications.