• 제목/요약/키워드: pn junction

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Depth-dependent EBIC microscopy of radial-junction Si micropillar arrays

  • Kaden M. Powell;Heayoung P. Yoon
    • Applied Microscopy
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    • v.50
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    • pp.17.1-17.9
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    • 2020
  • Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

Polymer PN Junction by low Energy Double Implantation Technique

  • Jeong, Yong-Seok
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.721-724
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    • 2011
  • Polymer base organic PN junction with various ion types was studied. Low-energy ion implantation technique(~keV) is very useful in physical doping on PPP(Polyparaphenylene) polymer. By double implantation, effective organic PN junction was achieved. The best obtained electrical I-V property was rectification ratio which was about 10000. However, still have problems in low junction current density.

Study on the pn Junction Device Using the POCl3 Precursor (POCl3를 사용한 pn접합 소자에 관한 연구)

  • Oh, Teresa
    • Journal of the Korean Vacuum Society
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    • v.19 no.5
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    • pp.391-396
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    • 2010
  • The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor to research the characteristic of interface at pn junction. The sheet resistance was decreased in accordance with the increasing the diffusion process time for n-type doping on p-type Si wafer. The electron affinity at the interface in the pn junction was decreased with increasing the amount of n-type doping and the sheet resistance also decreased. Consequently, the drift current due to the generation of EHP increased because of low potential barrier. The efficiency and fill factor were increased at the solar cell with increasing the diffusion process time.

Fabrication and Properties of pn Diodes with Antimony-doped n-type Si Thin Film Structures on p-type Si (100) Substrates (p형 Si(100) 기판 상에 안티몬 도핑된 n형 Si박막 구조를 갖는 pn 다이오드 제작 및 특성)

  • Kim, Kwang-Ho
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.2
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    • pp.39-43
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    • 2017
  • It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

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Optimized doping density and doping profile of pn junction for using high power device

  • Jang, Geon-Tae
    • Proceeding of EDISON Challenge
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    • 2016.03a
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    • pp.347-349
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    • 2016
  • 본 논문에서는 dopant density에 의존적인 pn junction의 breakdown 특성을 향상시키기 위하여, doping density와 doping profile에 대하여 분석했다. Doping density와 doping profile은 역방향 junction breakdown voltage를 결정하는 중요한 요소인 공핍영역의 두께와 공핍영역 내에 인가되는 electric field를 결정한다. Uniform doping profile과 Gaussian doping profile을 비교했고, 고전압 환경에서 사용할 수 있는 소자를 제작하는데 더욱 적절한 doping profile과 doping 농도에 대해 기술했다.

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Analytical Model of Breakdown Voltages for Abrupt pn Junctions in III-V Binary Semiconductors (III-V족 반도체에서 계단형 pn 접합의 해석적 항복전압 모델)

  • 정용성
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.1-9
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    • 2004
  • Analytical expressions for breakdown voltages of abrupt pn junction in GaP, GaAs and InP of III-V binary semiconductors was induced. Getting analytical breakdown voltage, effective ionization coefficients were extracted using ionization coefficient parameters for each materials. The result of analytical breakdown voltages followed by ionization integral agrees well with numerical and experimental results within 10% in error.

Improved Rs Monitoring for Robust Process Control of High Energy Well Implants

  • Kim, J.H.;Kim, S.;Ra, G.J.;Reece, R.N.;Bae, S.Y.
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2007.06a
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    • pp.109-112
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    • 2007
  • In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

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Characteristics of Electroplated Ni Thick Film on the PN Junction Semiconductor for Beta-voltaic Battery (베타전지용 PN 접합 반도체 표면에 도금된 Ni 후막의 특성)

  • Kim, Jin Joo;Uhm, Young Rang;Park, Keun Young;Son, Kwang Jae
    • Journal of Radiation Industry
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    • v.8 no.3
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    • pp.141-146
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    • 2014
  • Nickel (Ni) electroplating was implemented by using a metal Ni powder in order to establish a $^{63}Ni$ plating condition on the PN junction semiconductor needed for production of beta-voltaic battery. PN junction semiconductors with a Ni seed layer of 500 and $1000{\AA}$ were coated with Ni at current density from 10 to $50mA\;cm^{-2}$. The surface roughness and average grain size of Ni deposits were investigated by XRD and SEM techniques. The roughness of Ni deposit was increased as the current density was increased, and decreased as the thickness of Ni seed layer was increased. The results showed that the optimum surface shape was obtained at a current density of $10mA\;cm^{-2}$ in seed layer with thickness of $500{\AA}$, $20mA\;cm^{-2}$ of $1000{\AA}$. Also, pure Ni deposit was well coated on a PN junction semiconductor without any oxide forms. Using the line width of (111) in XRD peak, the average grain size of the Ni thick firm was measured. The results showed that the average grain size was increased as the thickness of seed layer was increased.

Nano-gap Trench Etching using Forward Biased PN Junction for High Performance MEMS Devices (고성능 MEMS 소자를 위한 순방향 전극이 걸린 PN 접합을 이용한 나노 간격 홈의 식각)

  • Jeong, Jin-Woo;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.833-836
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    • 2005
  • Nano-gap trench is fabricated by the novel electrochemical etching technique using forward biased PN junction formed at the backside of the wafer. PN junction is formed using boron nitride wafer and the concentration of the boron doping is the high value of $1{\times}10^{19}$ $cm^{-3}$. The electro-chemical etching is performed in the 5% HF solution under the forward bias voltage of $1{\sim}2V$. The relationship between the etch rate of the trench and the voltage of the forward bias is investigated and the dependence of the gap for the voltage also examined. The etch rate increase from 0.027 ${\mu}m/min$ to 0.031 ${\mu}m/min$ as the value of the applied voltage increase from 1V to 2V, but the the gap is kept constant value of 40 nm.

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On the Breakdown Voltage and Optimum Drift Region Length of Silicon-On-Insulator PN Diodes (SOI PN 다이오드의 항복전압과 최적 수평길이에 관한 연구)

  • 한승엽;신진철;최연익;정상구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.12
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    • pp.100-105
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    • 1994
  • Analytical expressions for the breakdown voltage and the optimum drift region length (L$_{dr}$) of SOI (Silicon-On-Insulator) pn diodes are derived in terms of the doping concentration and the thickness of the n- drift region and the buried oxide thickness. The optimum L$_{dr}$ is obtained from the condition that the breakdown voltage of the vertical electric field of n+n- junction equals to the of the lateral electric field of n+n-p+ junction. Analytical results agree reasonably with the numerical simulations using PISCESII.

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