• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.573-574
• /
• 2006

A low-power power-aware scalable pipelined Booth recoded multiply & Accumulate unit (PA-MAC) detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication and accumulation operation. The multiplication mode is determined by the dynamic - range detection unit. For the computations, although an area of the proposed PA-MAC is lager than a non-scalable MAC respectively, the proposed PA-MAC proves to be globally more power efficient than a non-scalable MAC.

• Proceedings of the KIEE Conference
• /
• 1998.11b
• /
• pp.575-578
• /
• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

• ETRI Journal
• /
• v.39 no.5
• /
• pp.632-642
• /
• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.11a
• /
• pp.534-537
• /
• 1999

This paper describes a design of pipelined adaptive decision-feedback equalizer (PADFE) for high bit-rate wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of ADFE by using delayed least-mean-square (DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of ADFE including filter laps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters (filter tap, coefficient and internal bit-width, etc.) and equalization performance (bit error rate, convergence speed, etc.) are analyzed by algorithm-level simulation using COSSAP. The PADFE was designed using VHDL and Synopsys, and mapped into two ALTERA FLEX10k100 FPGAs.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.2
• /
• pp.291-297
• /
• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.8
• /
• pp.2152-2162
• /
• 1997

We developed an approach to automatically synthesize time-stationary controllers for a given pipelined data path of Application Specific Integrated Circuits (ASICs). This work consists of automated production of control specifications and Finite State Machine (FSM) Optimization. A FSM controller is implemented by performing horizontal partitioning so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization, and the results indicate large savings in total controller area.

• Journal of Korea Multimedia Society
• /
• v.11 no.6
• /
• pp.816-827
• /
• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.148-149
• /
• 2014

This paper evaluates performance of a pipelined dynamic bandwidth allocation scheme for XG-PON (10-Gbps-capable passive optical network) system for power saving. Under self-similar traffic and balanced input loads, we evaluate performance of XG-PON systems using computer simulations.

• Progress in Superconductivity and Cryogenics
• /
• v.8 no.2
• /
• pp.17-19
• /
• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.149-159
• /
• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.