• 대한전자공학회논문지SD
• /
• 제42권7호
• /
• pp.1-4
• /
• 2005

본 논문에서는 병렬식 광 인터컨넥트 응용을 위한 멀티채널 광수신기 어레이를 구현한다. 0.8$\mu$m Si/SiGe HBT 공정을 이용하여 설계한 수신기 어레이는 4채널의 전치증폭기 (transimpedance amplifier 혹은 TIA)와 PIN 광다이오드를 포함하는데, TIA는 일반적인 에미터 접지 (common-emitter 혹은 CE) 입력단을 취한다. 측정결과로서, CE TIA 어레이는 3.9GHz 주파수 대역폭과 62dB$\Omega$ 트랜스 임피던스 이득, 7.SpA/sqrt(Hz) 평균 노이즈 전류 스펙트럼 밀도 및 -2SdB 채널 간 crosstalk 성능을 가지며, 4채널 전체 모듈이 40mW 전력소모를 보인다.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2008년도 추계학술대회B
• /
• pp.2053-2058
• /
• 2008

It was investigated thermal performances on two array types of a serial circulation and a two-way parallel circulation for six water-cooled cold plates covered with non-metallic material (polycarbonate, PC) to reduce weight of the cooling devices for humanoid robot cooling. Six cold plates attached on $10{\times}10\;mm^2$ copper base : $0.5{\times}0.5\;mm^2$ pin-finned surfaces of 1.5 mm high with 0.5 mm array spacing, was mounted on six copper heating blocks with isothermal conditions of $50{\sim}90^{\circ}C$, respectively. In order to compare thermal characteristics according to two circulation types, the surface temperatures of heating blocks and the cooling water temperatures at inlets and outlets of cold plates were measured. From the results, it was found that a two-way parallel circulation was better performance than a serial circulation in terms of total thermal resistance, total heat transfer rate, and surface temperature rises from $1^{st}$ heating block to last one for six multiple cold plates.

• 반도체디스플레이기술학회지
• /
• 제15권3호
• /
• pp.12-17
• /
• 2016

In this study, numerical simulations for the conjugate heat transfer of air with a heat-sink of CPU were conducted. The heat-sink consisted of many fins of cylinder shape and the effect of the number of fins on the cooling performance of the heat sink was investigated. Grid independent solutions were obtained to compare the maximum temperature of the heat-sink for various conditions. It was found that maximum temperature of the heat-sink asymptotically approached 310K as the number of fins went to infinity. The energy exchange of air with the heat-sink was found to be nearly independent on the number of fins.

• 대한전자공학회논문지SD
• /
• 제42권8호
• /
• pp.53-60
• /
• 2005

최근 낮은 기가비트급 광통신 집적회로의 구현에 sub-micron CMOS 공정이 적용되고 있다. 본 논문에서는 표준 0.35mm CMOS 공정을 이용하여 4채널 3.125Gb/s 차동 전치증폭기 어레이를 구현하였다. 설계한 각 채널의 전치증폭기는 차동구조로 regulated cascode (RGC) 설계 기법을 이용하였고, 액티브 인덕터를 이용한 인덕티브 피킹 기술을 이용하여 대역폭 확장을 하였다 Post-layout 시뮬레이션 결과, 각 채널 당 59.3dBW의 트랜스임피던스 이득, 0.5pF 기생 포토다이오드 캐패시턴스에 대해 2.450Hz의 -3dB 대역폭, 그리고 18.4pA/sqrt(Hz)의 평균 노이즈 전류 스펙트럼 밀도를 보였다. 전치증폭기 어레이의 공급전원은 단일전압 3.3V 이고, 전력소모는 92mw이다. 이는 4채널 RGC 전치증폭기 어레이가 저전력, 초고속 광인터컨넥트 분야에 적합함을 보여준다.

• Journal of Mechanical Science and Technology
• /
• 제18권9호
• /
• pp.1572-1581
• /
• 2004

The purposes of the paper are to apply the axiomatic design methodology to the design of PBGA package with polyimide coating under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by stress analysis. The analysis model is a 256-pin perimeter Plastic Ball Grid Array (PBGA) package with the polyimide coating surrounding chip and above surface of BT-substrate. The polyimide coating is suggested to depress the maximum stresses occurred on the stress concentration positions. The axiomatic design methodology is proved to be useful to find the more reliable design conditions for PBGA package. Finally, the optimal values of design variables to depress the stress in the PBGA package are obtained.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.1141-1144
• /
• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• 대한전기학회논문지
• /
• 제35권9호
• /
• pp.375-379
• /
• 1986

The HCP(Hypocycloidal Pinch) device for plasma focus was modified for a pumping source of the dye laser, and the spectral distribution and time behavior of its light pulses were investigated by using a UV spectrometer, 70 MHz CRO and Si-PIN photodiode detector. An array of multiple stages of HCP and narrower electrode gaps were chosen in order to make a more uniform discharge along the HCP axis. The possible spectral range for the pumping of dye laser is 360-620nm, when the HCP is operated at 5-8kv of apllied voltage and 50-150Torr of Ar fill gas pressure. The rise-time and FWHM of light pulses from the HCP are 5us and 30-50us respectively when it is operated under the same conditions as above.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.422-423
• /
• 2005

RF Micro switches is a miniature device or an array of integration devices and mechanical components and fabricated with Ie batch-processing techniques. RF Micro switches application area are in phased arrays and reconfigurable apertures for defence and telecommunication systems, switching network for satellite communication, and single-pole double throw switches for wireless application. Recently, RF Micro switches have been developed for the application to the milimeter wave system. RF Micro switches offer a substantilly higher performance than PIN diode or FET switches. In this paper, SPDT(single-pole-double-throw) switch are designed to use 10 GHz. Actuation voltage and displacement are simulated by tool.

• Tribology and Lubricants
• /
• 제25권1호
• /
• pp.25-30
• /
• 2009

본 연구에서는 pin-on-disk 마찰 시험기를 통하여 Hexagonal 배열 $40{\mu}m$ Dimple 패턴의 효과를 실험하였다. 마찰 실험은 미끄럼 속도가 $0.06{\sim}0.34m/s$로 하였으며 마찰하중은 $20{\sim}100\;N$의 범위로 하였고, Dimple의 밀도는 $10{\sim}25%$의 범위로 제작하여 실험을 행하였다. 일반적으로 속도가 증가하고 하중이 감소할수록 마찰계수는 감소하는 경향을 나타내었으며, Dimple에 의한 마찰저감 효과는 속도가 $0.14{\sim}0.26m/s$의 범위에서 나타났다. $40{\mu}m$ Hexagonal 배열 Dimple 패턴의 마찰 특성에서는 밀도가 12.5%에서 가장 좋은 경향을 나타내었다.

• Journal of Welding and Joining
• /
• 제17권2호
• /
• pp.61-65
• /
• 1999

Because of the need for packages which accommodate high pin count, high density and high speed device, PBGA(plastic ball grid array) package gets more spotlight. But the substrate material which is used for PBGA package is in nature susceptible to moisture penetration. The objective of the study is to find out the path of delamination in the stacked structure of substrate. To increase the adhesion between the cooper laminate and PSR(photo solder resist) which is the weakest part, experiments were performed by changing parameters of printing pre-treatment and post-treatment process. As a result of experiments, the factor effects on the adhesion between the cooper laminate and PSR is caused by all of the pre-treatment and post-treatment condition. A considerable change was observed depending on the amount of UV irradiation after thermal cure which is typical of printing post-treatment condition rather than pre-treatment condition.