• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.3
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• pp.452-456
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• 2016

In this paper, a dual-channel readout amplifier array is realized in a standard $0.18{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode with 0.9 A/W responsivity and a 1.0 Gb/s readout amplifier(ROA). The proposed ROA shares the basic configuration of the previously reported feedforward TIA, except that it exploits a replica input to exclude a low pass filter(LPF), thus reducing chip area and improving integration level, and to efficiently reject common-mode noises. Measured results demonstrate that each channel achieves $70dB{\Omega}$ transimpedance gain, 829 MHz bandwidth, -22 dBm sensitivity for $10^{-9}BER$, -34 dB crosstalk between adjacent channels, and 45 mW power dissipation from a single 1.8 V supply.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.119-124
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• 1998

Block Matching Motion Estimation(BMME) Algorithm is demands a very large amount of computing power and have been proposed many fast algorithms. These algorithms are many problem that larger size of VLSI scale due to non-localized search block data and problem of non-reuse of input data for each processing step. In this paper, we designed systolic arry of high processing capacity, constraints input output pin size and reuse of input data for small VLSI size. The proposed systolic array is optimized memory access time because of iterative reuse of input data on search block and become independent of problem size due to increase of algorithm's parallelism and total processing elements connection is localized spatial and temporal. The designed systolic array is reduced O(N6) time complexity to O(N3) on moving vector and has O(N) input/output pin size.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.10
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• pp.1137-1144
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• 2012

In this paper, a 2.6 GHz switched parasitic array(SPA) antenna is designed to resolve the device interference in the femtocell. The designed SPA antenna structure consists of a central ${\lambda}/4$ monopole antenna as a radiator and surrounding four parasitic elements operating as a reflector or a director depending on the switching state. In addition, open state monopoles around the parasitic elements are placed to improve the directivity. The designed antenna utilizes RF FETs as switching elements instead of conventional PIN diodes, which enables beam steering with a simple structure consuming low power. To select the proper FET switch, the performance of the SPA antenna depending on the switch characteristics is analyzed. The fabricated antenna has 65 mm radius and 35 mm height, which shows about 15 dB front-back-ratio(FBR) at 2.6 GHz and enables eight-directional beam steering.

• Korean Journal of Optics and Photonics
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• v.25 no.1
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• pp.21-28
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• 2014

In this paper a Super Multi-view display method using a pinhole array with full parallax was proposed. The proposed method was simulated and its parameters analyzed. Also, the distribution and irradiance of light through each pinhole on the retina receiver, according to the change of crystalline lens focal length, were found by simulation. As a result, an image free of blurring was obtained while the crystalline lens focused on the depth plane of the three-dimensional image created by the imaging lens.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.1
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• pp.35-39
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• 2013

This paper reports numerical study results with respect to the thermal behavior of a natural convection cooled hybrid fin heat sink (HFH). The HFH consists of hybrid fins, hollow pin fins integrated with plate fins. The thermal performance of the HFH was numerically investigated by employing a commercial CFD software package and compared with that of the pin fin heat sink (PFH). Numerical study has found that array-based and mass-based heat transfer coefficients of the HFH are 12% and 37% greater than those of the PFH, respectively. Extended surface area and lighter weight may explain the better thermal performance of the HFH than the PFH.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.559-562
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• 1999

In this paper, we developed on internet based assembly information display system for the blind. The system is consist of hardware and software. The hardware is consist of a voice synthesis device and a tactile display for character information, and the software is consist of internet web browser for the blind and braille program. The tactile-device system consists of a control unit, pin array, pin generator, serial port, and a power supply. The pin exerted by a electromagnetic method, solenoid. The internet web browser separates the character and image from internet web page, and character information in the web page is converted to braille and fed to sound system. Also the image in the web page can be printed developed tactile display. As the results of experiment, the blind could access the internet web site by using this system and understand various internet information.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.54-62
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• 2015

This paper describes the design and fabrication of an electronically rotated Tactical Air Navigation(TACAN) antenna using parasitic elements and PIN diode switches. We used parasitic elements arranged in a circular array and PIN diode switches to electronically rotate the antenna instead of employing a mechanically rotated antenna using motor. The antenna's physical characteristics and design features to generate the cardioid pattern and nine-lobe pattern including bearing information are described and simulated. The measured result shows a very good agreement with simulation and meets the specification of MIL-STD-291C.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.93-96
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• 2001

Tactile display devices use an array of pins mounted in the form of a matrix to present three-dimensional shapes to the user by raising and lowering. With a denser matrix of mounted pins, it can be expected that shape identification will be become easier and the time required for identification will also become shorter, but that problems of difficulty in fabrication will arise. It is necessary to consider such trade-offs in the development of such devices. This study conducted experiments to study the effect of pin pitch on shape identification as Part of the fundamental investigation of this subject. The experiment used three tactile display devices with pin pitches of In, 2mm and 3mm for geometrical shape identification, with response time and rate of misidentification taken as the performance data. Surfaces, edgs and vertices of three-dimensional shapes were used as the shape primitives for displayed shapes and several of each type were selected for presentation. The results obtained revealed that performance has different relationships to pin pitch with different shape primitives.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.