• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.6
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• pp.1043-1048
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• 2011

In this paper, a newsynchronization technique applied to burst-mode communication is proposed. A synchronization technique is to estimate carrier frequency and phase offsets in a noisy channel environment. A fundamental problem for estimating the parameters(carrier phase and frequency offsets) in burst-mode transmission is that the ways of pursuing estimation accuracy and transmission efficiency are always trade-off. To solve this problem, a new carrier recovery technique is proposed to improve the transmission efficiency with reliable performance especially at low S/N. In the proposed technique, the synchronization parameters are first estimated based on a data-aided feed-forward estimation scheme. Then, a phase tracker using decision-directed DPLL estimates the phase offset for the data portion of the burst data. From simulation results, it shows fast synchronization with shorter preamble maintaining reasonable BER performance at low S/N.

• The Journal of the Acoustical Society of Korea
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• v.41 no.2
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• pp.159-165
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• 2022

In this paper, a frame synchronization structure for the Binary Phase Shift Keying (BPSK) modulation method in underwater acoustic communication was proposed. The proposed frame synchronization structure is largely divided into two. First, the approximate position and frequency offset of the frame are obtained by non-coherent correlation and sliding Fast Fourier Transform (FFT) method. Second, after compensating for the frequency error to the received signal, the exact position of the frame is obtained by coherent correlation method. Maritime experiments were conducted to confirm the performance of the 2-STEP frame synchronization structure. It was showed that the limitations of the non-coherent correlation and sliding FFT method can be verified when the power of the received signal was greatly reduced due to the channel characteristics. As a result, stable frame synchronization could be obtained by compensating for the frequency error and then using the coherent correlation method.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.4
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• pp.51-57
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• 2013

Research on calibration of array antenna has become a hot spot in the area of signal processing and it is necessary to obtain the phase mismatch of each antenna channel. This paper presents a new calibration method for an array antenna system. In order to calibrate the phase mismatch of each antenna channel, we used primary synchronization signal (PSS) which exists in LTE downlink frame. Primary synchronization signal (PSS) is based on a Zadoff-Chu sequence which has a good correlation characteristic. By using correlation calculation, we can extract primary synchronization signal (PSS). After extracting primary synchronization signal (PSS), we use it to calibrate and reduce the phase errors of each antenna channel. In order to verify the new array antenna calibration algorithm which is proposed in this paper, we have simulated the proposed algorithm by using MATLAB. The array antenna system consists of two antenna elements. The phase mismatch of first antenna and second antenna is calculated accurately by proposed algorithm in the experiment test. Theory analysis and MATLAB simulation results are shown to verify the calibration algorithm.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.160-163
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• 1986

In a digital telecommunication network, the clock synchronization is inevitable to prevent the data loss caused by inconsistency of clock frequencies. This paper descries the considerations necessary for synchronization and the implementation of the clock synchronization system using digital processing phase locked loop method in TDX-1 switching system.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.315-317
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• 2003

Neural oscillator is applied in oscillatory systems (Analysis of image information, Voice recognition. Etc...). If we apply established EBPA(Error back Propagation Algorithm) to oscillatory system, we are difficult to presume complicated input's patterns. Therefore, it requires more data at training, and approximation of convergent speed is difficult. In this paper, I studied the neural oscillator as synchronized states with appropriate phase relation between neurons and recognized the Korean alphabet using Neural Oscillator Phase model Synchronization.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1939-1949
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• 2016

This paper presents an alternative frequency adaptive grid synchronization technique named HDN-FLL, which can accurately extract the fundamental positive- and negative-sequence components and interested harmonics in adverse three-phase grid voltage. The HDN-FLL is based on the harmonic decoupling network (HDN) consisting of multiple first order complex vector filters (FOCVF) with a frequency-locked loop (FLL), which makes the system frequency adaptive. The stability of the proposed FLL is strictly verified to be global asymptotically stable. In addition, the linearization and parameters tuning of the FLL is also discussed. The structure of the HDN has been widely used as a prefilter in grid synchronization techniques. However, the stability of the general HDN is seldom discussed. In this paper, the transfer function expression of the general HDN is deduced and its stability is verified by the root locus method. To show the advantages of the HDN-FLL, a simulation comparison with other gird synchronization methods is carried out. Experimental results verify the excellent performance of the proposed synchronization method.

• Journal of Korea Multimedia Society
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• v.18 no.4
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• pp.452-459
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• 2015

Three synchronization issues, i.e., phase, frequency, and symbol time, have to be properly controlled to achieve distributed beamforming gain. In this paper, the impacts of synchronization errors in distributed beamforming are analyzed for both single-carrier and OFDM systems. When the channel is constant over a symbol duration, the performance degradation due to phase offset is the same for both single-carrier and OFDM systems. For symbol timing offset in OFDM systems, high frequency subcarriers are more susceptible as compared to low frequency ones. Frequency offset is critical in OFDM systems since it leads to interference from the other subcarriers as well as power loss in the desired signal.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.624-628
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• 2008

This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.