• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.240-242
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• 2008

본 논문에서는 단상 PLL알고리즘 중 하나인 영점검출 방식에서의 순시제어 불능을 극복하기 위해 arcsin을 이용한 알고리즘을 제안하였다. 또한 시뮬레이션을 통해 영점검출과 비교하여 제안된 PLL알고리즘의 순시제어 가능성을 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• 전력전자학회논문지
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• 제20권1호
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• Journal of Power Electronics
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• 제13권5호
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• pp.884-895
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• 2013

In this paper, the Fourier-based PLL (Phase-locked Loop) is introduced with a new structure, capable of selective harmonic detection in single and three-phase systems. The application of the FB-PLL to harmonic detection is discussed and a new model applicable to three-phase systems is introduced. An analysis of the convergence of the FB-PLL based on a linear model is presented. Simulation and experimental results are included for performance analysis and to support the theoretical development. The decomposition of an input signal in its harmonic components using the Fourier theory is based on previous knowledge of the signal fundamental frequency, which cannot be easily implemented with input signals with varying frequencies or subjected to phase-angle jumps. In this scenario, the main contribution of this paper is the association of a phase-locked loop system, with a harmonic decomposition and reconstruction method, based on the well-established Fourier theory, to allow for the tracking of the fundamental component and desired harmonics from distorted input signals with a varying frequency, amplitude and phase-angle. The application of the proposed technique in three-phase systems is supported by results obtained under unbalanced and voltage sag conditions.

• 전력전자학회논문지
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• 제9권4호
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• pp.356-363
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• 2004

본 논문에서는 무정전 전원장치와 같이 일정전압 일정주파수(constant voltage and constant frequency; CVCF) 운전에 사용되는 단상 PWM 인버터의 정밀 전압제어 기법을 다루었으며 정상상태에서 전압 오차를 최소화하기 위해 phase-locked loop(PLL) 기법을 이용한 새로운 전압 제어 방법을 제안하였다. 제안된 제어기법에서는 출력 커패시터 전압과 전류를 이용하여 PLL 보상기를 구성하였으며 주제어기에 PLL 보상기를 추가하여 출력 전압의 정상상태 성능을 개선하였다. 제안된 방법의 타당성을 검증하기 위하여 시뮬레이션과 실험을 수행하였으며, 그 결과 기존의 방법에 비해 정상상태 전압제어 성능과 Total Harmonic Distortion(THD)이 현저히 개선됨을 입증할 수 있었다.

• ETRI Journal
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• 제33권3호
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of Multimedia Information System
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• 제5권2호
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• 한국정보전자통신기술학회논문지
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• 제14권6호
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• pp.479-486
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• 2021

본 논문에서는 신호감지회로(Signal Sensing Circuit : SSC)를 추가하여 2개의 루프로 구성된 단일 커패시터 루프필터를 가진 극소형 위상고정루프(Phase Locked Loop : PLL)를 제안하였다. 위상고정루프 크기를 극단적으로 줄이기 위하여 가장 많은 면적을 차지하는 수동소자 루프필터를 극소형 단일 커패시터(2pF)로 설계하였다. 신호감지회로가 포함된 내부 부궤환 루프 출력이 외부 부궤환 루프의 단일 커패시터 루프필터 출력에 부궤환 역할을 하여 제안한 극소형 위상고정루프가 안정적으로 동작하도록 설계하였다. 위상고정루프 출력 신호 변화를 감지하는 신호 감지 회로는 루프필터의 커패시턴스 전하량을 조절하여 위상고정루프 출력 주파수의 초과 위상변이를 줄였다. 제안된 구조는 기존 구조에 비해 1/78 정도의 작은 커패시터를 가짐에도 불구하고 지터 크기는 10% 정도 차이가 난다. 본 논문의 위상고정루프는 1.8V 180nm 공정을 사용하였고, Spice를 통해 안정하게 동작하는 시뮬레이션 결과를 보여주었다.

• 한국전자파학회논문지
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• 제16권1호
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• pp.49-55
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• 2005

본 논문에서는 아날로그 위상 고정 루프(PLL: Phase Locked Loop)를 이용한 무선 LAN(Wireless Local Area Network)용 위상 고정 고조파 발진기(PLHO: Phase Locked Harmonic Oscillator)를 설계 및 제작하였다. 이 고조파 발진기는 Ring 공진기, 주파수 동조를 위한 바랙터 다이오드 그리고 위상 고정 루프 회로로 구성된다. 발진기의 8.5 GHz의 기본 주파수는 위상 고정 루프를 위한 귀환 신호로 이용되고 17.0 GHz의 2차 고조파는 출력으로 이용되므로 위상 고정 시스템에서 위상 비교를 위한 주파수 분배기를 한 단계 줄일 수 있다. 위상 비교기로는 샘플링 위상 검출기(SPD: Sampling Phase Detector)를 사용하여 위상고정 루프 회로를 간단히 하였다. 위상고정 고조파 발진기의 발진 출력은 17.0 GHz에서 2.17 dBm, 기본 주파수와 3차 고조파 억압 특성은 각각 -31.5 dBc, -29.0 dBc이다. 위상잡음은 각각 -87.6 dBc/Hz at 1 kHz와 -95.4 dBc/Hz at 10 kHz이다.