• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.552-559
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• 2002

The EM(Engineering Model) LO(Local Oscillator) is designed for Ka-band satellite transponder. The VCO(Voltage Controlled Oscillator) is implemented using a high impedance inverter coupled with dielectric resonator to improve the phase noise performance out of the loop bandwidth. The phase of VCO is locked to that of a stable OCXO(Oven Controlled Crystal Oscillator) by using a SPD(Sampling Phase detector) to improve phase noise performance in the loop bandwidth. This LO exhibits the harmonic rejection characteristics above 43.83 dBc and requires 15 V and 160 mA. The phase noise characteristics are performed as -102.5 dBc/Hz at 10 KHz offset frequency and -104.0 dBc/Hz at 100 KHz offset frequency, respectively, with the output power of 13.50 dBm$\pm$0.33 dB over the temperature range of -20~+7$0^{\circ}C$.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.890-893
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• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• 전기의세계
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• v.30 no.11
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• pp.717-727
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• 1981

The phase-locked loop technique developed in the 1930's has many advantages when applied to speed control. The speed control and analysis of a three phase induction motor using the PLL are described in this paper. In this system, the phase frequency detector (PFD) compares the actual motor speed from the pulses received from a shaft encoder and desired speed, and the difference adjusts the frequency of the inverter that feeds the motor, and excellent speed regulation in the order of 0.035(%) has been-obtained. A linear continuous model of the drive is developed and system response is analysed using conventional root locus techniques. Various compensating filters and feedback signals are considered and the need for addition of derivative feedback is shown. A sampled data model is used to study the effects of discrete PFD output. Stability limitson speed are predicted. A drive was implimented and experimental results are presented to verify theoretical predictions.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.3
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• pp.19-30
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• 2007

In this paper, we propose low-complexity implementation of orthogonal frequency division multiple access (OFDMA) timing delay detector with multiple receive antennas for broadband wireless access (BWA). First, in order to reduce the computational complexity, the detection structure which rotates the phase of the received ranging symbols is introduced. Second, we propose the detection structure with the N-point/M-interval fast Fourier transform structure and a frequency-domain average-power estimator for complexity reduction without sacrificing the system performance. Finally, simulation results for the proposed structures and complexity comparison of the existing structure with the proposed detectors are presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.685-691
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• 2003

This paper newly analyzes the effect of the phase noise in the frequency synthesizer on the performance of SFH/M-NCFSK system by standard frequency deviation(equation omitted) when noncoherent FSK demodulation of the square-law detector is considered. We derive the SER in the SFH system and analyze the effect of phase noise on the SFH/M-NCFSK system performance according to the hopping frequency spacing (1/T$\_$h/) and the variation of the standard frequency deviation (equation omitted). The required SNR is about 13.4 dB to meet Ps=10$\^$-3/ when the standard frequency deviation is about 4.0 Hz and the hopping frequency spacing (1/T$\_$h/) in the SFH/2-NCFSK system is 30. So, there is about 2.4 dB power penalty than the phase noise-free system. If the hopping frequency spacing 1/T$\_$h/ is under 30, the error floor may happen and SER considerably grows up. We show that the analytic results closely match with the simulation results.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.