• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.46-48
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• 2007

This paper presents research about improvement of fault detection algorithm in FRTU on the feeder of distribution system. FRTU(Feeder Remote Terminal Unit) is applied to fault detection schemes for phase fault, ground fault, and cold load pickup and Inrush restraint functions distinguish the fault current and the normal load current. FRTU is occurred FI(Fault Indicator) when current is over pick-up value also inrush current is occurred FRTU indicate FI. Discrete wavelet transform(DWT) analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate inrush current from the fault status by a gradient descent method. In this paper, fault detection is improved using voltage monitoring system with DWT and neural network. These data were measured in actual 22.9kV distribution system.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• 한국통신학회논문지
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• 제26권6B호
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• pp.848-855
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• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2228-2230
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• 2002

The research presented in this paper focuses on a method for the detection of High Impedance Fault(HIF). The method will use the Lifting and neural network system. HIF on the multi-grounded three-phase four-wires primary distribution power system cannot be detected effectively by existing over current sensing devices. These paper describes the application of lifting scheme to the various HIF data. These data were measured in actual 22.9kV distribution system. Wavelet transform analysis gives the frequency and time-scale information. The neural network system as a fault detector was trained to discriminate HIF from the normal status by a gradient descent method. The proposed method performed very well by proving the right state when it was applied staged fault data and normal load mimics HIF, such as arc-welder.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.845-848
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• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1998년도 학술발표대회 논문집 제17권 2호
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• pp.259-262
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• 1998

In this paper, we have studied measurement technique for inhomogeneous residual stress using acoustic microscopy with quadrature detector. In experiment, aluminum tensile specimen with the flaw has been made and loaded by Instrone. A spherical typed acoustic transducer of center frequency 5MHz has been used for sending a longitudinal acoustic wave into a stressed specimen. It has been shown in experimental results that the phase has largely changed around the flaw that residual stress has been largely distributed and acoustic microscopy has been used in the field of residual stress measurement.

• 한국광학회지
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• 제10권5호
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• pp.357-363
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• 1999

다중산란매질의 광학계수를 측정하기 위하여 광세기의 변화와 위상차이를 동시에 측정하는 주파수 영역 분광장치를 구성하고, 산란과 흡수가 다른 매질 조건하에서 진폭 변조된 광을 입사시킨 후 후방 산란광의 교류 및 위상지연 성분을 heterodyne 검지 방법을 이용하여 측정하였다. 실험을 통하여 산란자와 흡수체의 농도가 증가함에 따라 흡수계수와 수송산란 계수는 선형적으로 증가함을 확인할 수 있었으며, 흡수계수와 수송산란계수를 확산이론을 이용하여 구할 수 있었다. 광원과 검출기의 거리, 변조주파수에 따라 측정 가능한 광학계수의 범위를 분석하였다. 레이저 다이오드를 사용하는 소형화된 이 장치는 생체조직과 같은 다중 산란매질의 비침습적 광학계수 측정에 이용될수 있으리라 기대된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.