• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• ETRI Journal
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• 제24권2호
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• pp.161-171
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• 2002

This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2005년도 동계학술발표대회 논문집
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• pp.433-438
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• 2005

An AHX(Accumulator Heat eXchanger) consists of a commercial accumulator and an inner heat exchanger located inside of the accumulator. The AHX is used in multi air-conditioners to assure the liquid-phase refrigerant entering into the expansion device. This purpose is achieved by heat transfer between the refrigerant leaving the evaporator and the refrigerant leaving the condenser. In this study, the effects of AHX on the performance of a refrigeration system using H-22 were measured and the test results were analyzed. The operating characteristics of the refrigeration system with the installation of AHX were quite different from those without the installation of AHX. Therefore, it is required to find an optimum refrigerant charging amount and optimum operating conditions, when AHX is installed in the refrigeration system with an fixed area expansion device such as a capillary tube.

• 설비공학논문집
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• 제18권5호
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• pp.418-425
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• 2006

An AHX (Accumulator Heat exchanger) consists of a commercial accumulator and an inner heat exchanger located inside of the accumulator. The AHX is used in multi air-conditioners to assure that liquid-phase refrigerant enters into the expansion device. This purpose is achieved by heat transfer between the refrigerant leaving the evaporator and the refrigerant leaving the condenser. In this study, the effects of AHX on the performance of a refrigeration system using R-22 were measured and the test results were analyzed. The operating characteristics of the refrigeration system with the AHX are considerably different from those without the AHX. Therefore, it is required to determine optimum refrigerant charge and optimum operating conditions when the AHX is used in the refrigeration system having a constant flow-area expansion device such as capillary tube.

• 한국ITS학회 논문지
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• 제6권2호
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• pp.126-137
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• 2007

본 논문에서는 새로운 ROM 압축방식을 사용한 저전력 직접 디지털 주파수 합성기를 제안하고 낮은 클럭에서 동작하는 위상 누적기를 병렬로 연결하여 높은 주파수를 생성하는 위상-사인 변환기를 설계한다. ROM크기를 줄이기 위해 사인파를 양자화 할 때 일련의 차동 양자화 기술을 응용, 변형하여 양자화 ROM(Quantized ROM : Q-ROM과 차동 ROM(Differential ROM : D-ROM)을 사용하는 QD-ROM 압축방식을 제안한다. 이를 사용함으로써 67.5%의 ROM 사이즈를 감소시킬 수 있고 ROM의 크기를 줄여 전력 소모를 줄일 수 있다.

• 대한전자공학회논문지
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• 제26권12호
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• pp.2046-2054
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• 1989

Improved algorithms are presented to design linear phase digital FIR filters with coefficients of +1,0,-1 only followed by a multiple integrator. It has been shown that the existing linear phase filter design concept for the single integrator(or, accumulator)case can be extended to the case of the multiple integrator. Linear phase conditions for the multiple integrators are summarized. Filter design methods with double or triple integrator are exploited in datail and its computer simulation results are presented to deduce the advantages of multiple integrator to the single integrator.

• 융합신호처리학회논문지
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• 제12권4호
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• pp.291-297
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• 2011

본 논문에서는 DPCM 방식의 차동 양자화 기술 및 병렬 기법을 응용하여 새로운 ROM 압축방식을 사용한 고속의 저 전력 직접디지털 주파수 합성기를 제안하고 FPGA를 사용하여 설계 및 제작한다. ROM 크기를 줄이기 위해 사인파를 표본화하여 양자화된 값을 양자화 ROM(Quantized ROM : Q-ROM)에 저장하고 각 표본화 사이클 차동 양자화하여 차동 ROM(Differential ROM : D-ROM)에 저장한다. 또한 낮은 클럭에서 동작하는 위상 누적기를 병렬로 2개 연결하여 높은 주파수를 생성하는 위상-사인 변환기를 설계 및 제작한다. 이를 사용함으로써 67.5%의 ROM 사이즈를 감소시킬 수 있고 ROM의 크기를 줄여 전력 소모를 줄일 수 있을 뿐만 아니라 고속의 직접 디지털 주파수 합성기를 설계 및 제작할 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.275-275
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• 2000

This paper designs a digital correlator for the integrated GPS/GLONASS receiver consisting of DCO, carrier cycle counter, code generator, code phase counter, mixer, epoch counter, accumulator. It is designed using Verilog-HDL(Verilog-Hardware Description Language) and synthesized using EDA(Electronic Design Automation) tools. The performance of the designed digital correlator is verified by the functional simulation and real satellite tracking experiments.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2033-2038
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• 2008

The CPLs(capillary pumped loops) are two phase heat transfer devices which enable active control of operating temperature of heat absorbing elements(or evaporators). Although the CPLs gain increasing interests as promising heat transfer devices for future missions such as spacecraft and commercial applications, their intrinsic complexity in operating principles makes the widespread use of these devices difficult. The key element and main cause of this complexity in operating principles is the two phase hydrodynamic accumulator or reservoir which controls the saturation state of the remaining loop and, particularly for the CPLs, it is separated from the evaporator. Thus, in this study, the operating characteristics of the CPL is investigated experimentally and theoretically. Mainly focusing on the role of reservoir the thermodynamic operating principle is examined first and the experimentally obtained steady state and transient state operating characteristics are discussed in detail.

• 한국정밀공학회지
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• 제21권9호
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• pp.103-110
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• 2004

Pressure ripples yield noise and vibration in hydraulic pipelines, which are inevitably generated by a fluctuation of flow rate in the pump mechanism, and such noise and vibration deteriorate the stability and accuracy of hydraulic systems. To reduce the pressure ripples, accumulator and hydraulic attenuator are normally used. In this study, parallel pipeline with a bent-axis piston pump is introduced to a hydraulic pipe system as a method for reducing the pressure ripples and using the transfer matrix method, the dynamic characteristics of the pipe system are analysed and compared with experimental results. The results show that the phase interference using parallel pipeline with a bent-axis piston pump is effective to reduce the pressure ripples in the hydraulic pipelines.